 Xiaochang WuandKunshang Ji
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8c8b1825eb
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[XPU] Enable multiple key kernels for sparse attention (#37888)
Signed-off-by: Xiaochang Wu <xiaochang.wu@intel.com>
Signed-off-by: Wu, Xiaochang <xiaochang.wu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-05-22 12:02:51 +08:00 |
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Yan MaandKunshang Ji
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be0dcc29dc
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[XPU] remove q/k/v force contiguous for flash_attn (#40356)
Signed-off-by: Yan Ma <yan.ma@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-05-09 01:19:05 +00:00 |
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Kunshang Ji
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2ceea42958
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[XPU] use xpu topk topp sample kernel (#39285)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-05-05 18:05:17 +08:00 |
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Yuwen ZhouandKunshang Ji
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4c34b2f6fc
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[XPU] Enable torch.compile for XPU GDN attention (#39466)
Signed-off-by: yuwenzho <yuwen.zhou@intel.com>
Signed-off-by: Yuwen Zhou <yuwen.zhou@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-04-24 16:26:16 +08:00 |
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Xinyu ChenandKunshang Ji
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55842a8d69
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[XPU]fake impl for xpu fp8_gemm (#39984)
Signed-off-by: Xinyu Chen <xinyu1.chen@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-04-18 08:53:56 +08:00 |
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zofia
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fc701c8058
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[XPU][MXFP4] add mxfp4 quant op for XPU (#39857)
Signed-off-by: Zhu, Zufang <zufang.zhu@intel.com>
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2026-04-15 12:28:19 +00:00 |
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Xinyu ChenandKunshang Ji
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639402f5a2
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Support FP8 KVCache on XPU (#37731)
Signed-off-by: Xinyu Chen <xinyu1.chen@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-04-12 03:53:32 +00:00 |
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zofiaandKunshang Ji
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ad3304425b
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[XPU] add xpu backend implementation of mxfp8 quant (#38682)
Signed-off-by: Zhu, Zufang <zufang.zhu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-04-08 08:30:35 +08:00 |
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Kunshang Ji
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14771f7150
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[XPU] support MLA model on Intel GPU (#37143)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-03-25 17:43:42 +08:00 |
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Tianmu Li
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47b7af0d87
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[Feat] Enable CompressedTensorW4A8Int for XPU (#37207)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
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2026-03-20 02:34:28 +00:00 |
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zhao, zhenhui
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4af9ed21cb
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[Bugfix](xpu): prevent “selected index k out of range” in TP decode path (#37259)
Signed-off-by: zhenzhao <zhenzhao@habana.ai>
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2026-03-17 11:14:07 +00:00 |
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Wang, Yiting
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68e1b711f1
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[XPU] Add deepseek_scaling_rope fused kernel (#36612)
Signed-off-by: yitingw1 <yiting.wang@intel.com>
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2026-03-16 12:35:08 +08:00 |
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Wuxun Zhang
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e584dce52b
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Add XPU MLA Sparse backend for DeepSeek v3.2 (#33230)
Signed-off-by: Zhang, Wuxun <wuxun.zhang@intel.com>
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2026-03-11 19:19:15 +08:00 |
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Chendi.Xue
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d72b0be33c
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[XPU]Fix for Qwen-OMNI crash (#35249)
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
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2026-02-25 07:31:07 -08:00 |
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Kunshang Ji
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cb9574eb85
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[XPU][9/N] clean up existing ipex code/doc (#34111)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-02-11 00:27:15 -08:00 |
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