 Woosuk KwonandCodex
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9b49f92344
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[Perf][DSV4.1] Overlap mHC coefficients for small TP batches (#57603)
Signed-off-by: Woosuk Kwon <woosuk@inferact.ai>
Co-authored-by: Codex <noreply@openai.com>
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2026-09-20 17:33:17 -07:00 |
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7d99c2c4fd
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[Feature][Humming] Humming feature integration (#56685)
Signed-off-by: jinzhen.ljz <jinzhen.ljz@antgroup.com>
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: Codex <noreply@openai.com>
Co-authored-by: mgoin <mgoin64@gmail.com>
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2026-09-20 08:11:01 -07:00 |
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Misha GoinandErinYin
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e5fce7b56b
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[Core][Kernel] Share persistent workspaces for Marlin and Humming (#57421)
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: ErinYin <liang.yin@daocloud.io>
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2026-09-20 17:28:33 +08:00 |
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siyuandIsotr0py
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4cc15f2121
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[Quantization] Let ModelOpt MXFP8 layers load pre-processed weights Purpose (#57316)
Signed-off-by: liusy58 <mg21330037@smail.nju.edu.cn>
Signed-off-by: Isotr0py <2037008807@qq.com>
Co-authored-by: Isotr0py <2037008807@qq.com>
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2026-09-19 09:16:39 +00:00 |
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Woosuk Kwon
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38537331d3
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[Bugfix][DSA] Avoid runtime JIT for offset candidate end buffers (#57667)
Signed-off-by: Woosuk Kwon <woosuk@inferact.ai>
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2026-09-19 00:27:11 -07:00 |
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Yuwen ZhouandLi, Jiang <jiang1.li@intel.com>
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b346479065
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[CPU] Add CPU FP8 W8A8 linear/MoE support (#49942)
Signed-off-by: yuwenzho <yuwen.zhou@intel.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-09-18 17:59:42 +08:00 |
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meng-amd
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6df2b1a8c6
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[Quantization] Support native Quark W4A16 INT4/UINT4 exports in vLLM (#48606)
Signed-off-by: HongWei Meng <HongWei.Meng@amd.com>
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2026-09-18 17:52:46 +08:00 |
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Woosuk KwonandCodex
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64563d0ec4
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[Bugfix][DSv4.1] Preserve NaN-scored candidate block indices (#57454)
Signed-off-by: Woosuk Kwon <woosuk@inferact.ai>
Co-authored-by: Codex <noreply@openai.com>
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2026-09-17 19:00:10 -07:00 |
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rasmithandShanshan Shen
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acc2ed2a5f
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[ROCm][CI][The Rock 10] Fix (MI355) Quantized Models failure on The Rock 10 with Triton 3.8.x (#54849)
Signed-off-by: Randall Smith <Randall.Smith@amd.com>
Co-authored-by: Shanshan Shen <467638484@qq.com>
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2026-09-17 15:20:35 -05:00 |
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danisereb
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2bdbbc8080
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[BugFix] Fix is_supported of cutlass FP8 linear (selected and fails on A100) (#55884)
Signed-off-by: Daniel Serebrenik <daserebrenik@nvidia.com>
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2026-09-16 12:31:43 -07:00 |
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Shanshan Shen
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bc0f47cd03
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[ROCm][Bugfix] Revert #56433 + #51692 to fix accuracy breakdown for DeepSeek-V4 (#57132)
Signed-off-by: Shanshan Shen <87969357+shen-shanshan@users.noreply.github.com>
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2026-09-16 18:58:23 +00:00 |
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Harry MellorandClaude Opus 5
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651a88c09a
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[CI] Ignore ruff D209, rejoin the docstrings it split, and silence incompatible-rule warnings (#57212)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-16 10:57:24 -07:00 |
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Rebecca LeeandCursor
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6ca2b23e22
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[ROCm] Expose kFp8DynamicTokenSym on AITER PTPC linears (#54248)
Signed-off-by: Rebecca Lee <rebecca.lee@amd.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-16 11:48:30 -05:00 |
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Harry MellorandClaude Opus 5
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8c1557a79c
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Add pydocstyle to the ruff rules (#52136)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Signed-off-by: Harry Mellor <hej.mellor@gmail.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-16 16:44:29 +00:00 |
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Harry MellorandClaude Opus 5
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5f203baedb
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[Docs] Split slash-combined docstring parameters (#57141)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-16 02:16:32 -07:00 |
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Li, Jiang
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b68408043d
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[Bugfix][CPU] Add per-tensor FP8 W8A16 kernel to fix Ministral crash on CPU (#56985)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-09-16 15:49:17 +08:00 |
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Jared WenandClaude Fable 5.1
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1257512305
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[DSA] Wire DeepGEMM sparse MQA logits into the DeepSeek V4.1 indexer (#56254)
Signed-off-by: Jared Wen <w13431838023@gmail.com>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
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2026-09-15 14:07:14 -07:00 |
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JohnQinAMDandClaude Opus 5
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ef5f7cd119
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[ROCm][DSv4.1][Perf] Dequantize the MXFP8 weight once when dot_scaled cannot be used (#56560)
Signed-off-by: JohnQinAMD <yanyuan.qin@amd.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-15 09:07:26 +08:00 |
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Fangzhou AiandCursor
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00972dfd72
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[ROCm][DSV4.1][Perf] Fold the mHC post step into the delayed pre projection (#56513)
Signed-off-by: Fangzhou Ai <fangzhou@semianalysis.ai>
Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-14 16:44:56 -05:00 |
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Netanel Haber
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d4ee7fe7a9
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[Quantization] Select linear backends per quantization (#51204)
Signed-off-by: Netanel Haber <58652339+netanel-haber@users.noreply.github.com>
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2026-09-14 16:24:18 -04:00 |
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Yongye Zhu
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5372e72a98
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[Perf][DSv4.1] Fold the mHC post block into the delayed pre projection (#56633)
Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
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2026-09-14 18:57:37 +00:00 |
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Matthias Gehre
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dc2e8f1157
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[ROCm][Perf] W4A16: keep skinny GEMM zero-points packed 4-bit (#54965)
Signed-off-by: Matthias Gehre <matthias.gehre@amd.com>
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2026-09-14 17:40:25 +08:00 |
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Li, Jiang
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79f0be21ff
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[Bugfix][CPU] Fix DeepSeek-R1 (FP8 MLA + MoE) correctness on CPU backend (#56773)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-09-14 17:30:28 +08:00 |
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Woosuk Kwon
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3b533197a9
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[Perf] Parallelize mHC pre-norm JIT warmup (#56683)
Signed-off-by: Woosuk Kwon <woosuk@inferact.ai>
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2026-09-13 18:58:20 -07:00 |
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Roberto L. CastroandCodex
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e52be1a62d
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[9/N][warmup][DSv4] Migrate MHC TileLang kernels (#50178)
Signed-off-by: LopezCastroRoberto <rocastro@redhat.com>
Signed-off-by: Roberto L. Castro <38211239+LopezCastroRoberto@users.noreply.github.com>
Co-authored-by: Codex <codex@openai.com>
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2026-09-12 17:25:23 -07:00 |
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Ayushman Singhandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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7bcca16729
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[Bugfix] Fix DeepGEMM FP8 warmup coverage (#56452)
Signed-off-by: Ayushman Singh <40520701+ayush1399@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-09-12 14:20:38 -04:00 |
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Roberto L. CastroandCodex
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120ec4ebd2
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[5/N][warmup][DSv4] Migrate NVIDIA CuTeDSL attention kernels (#53566)
Signed-off-by: LopezCastroRoberto <rocastro@redhat.com>
Co-authored-by: Codex <codex@openai.com>
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2026-09-12 00:05:59 -04:00 |
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Fangzhou AiandFangzhou Ai
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46d2b23ac5
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[ROCm][DSV4.1][Perf] Use AITER mHC for the delayed pre block (#56503)
Signed-off-by: Fangzhou Ai <fangzhou@semianalysis.ai>
Co-authored-by: Fangzhou Ai <fangzhou@semianalysis.ai>
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2026-09-12 00:35:48 +00:00 |
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Andy Lo
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dc07f1638f
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[Bugfix][MLA] Read sparse model settings from text config (#56160)
Signed-off-by: Andy Lo <andy@mistral.ai>
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2026-09-11 18:02:13 +00:00 |
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Matt
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b4da4d17ae
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[ROCm][Bugfix] Fix AITER preshuffled FP8 block-scale kernel (#56433)
Signed-off-by: Matthew Wong <Matthew.Wong2@amd.com>
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2026-09-11 11:44:57 +00:00 |
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Simon Danielsson
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7470082f57
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[ROCm][Perf] Add bpreshuffled blockscaled fp8 GEMM (#51692)
Signed-off-by: simondanielsson <simon.danielsson99@hotmail.com>
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2026-09-10 16:18:37 +00:00 |
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siyuandIsotr0py
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73fb19151f
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[Fast Start] Support fp4 (#55465)
Signed-off-by: Isotr0py <Isotr0py@outlook.com>
Co-authored-by: Isotr0py <Isotr0py@outlook.com>
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2026-09-10 13:22:17 +00:00 |
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9b959b8657
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[Model] DeepSeek-V4.1-Flash Model Definitions (#56228)
Signed-off-by: Roger Wang <hey@rogerw.io>
Signed-off-by: zjy0516 <riverclouds.zhu@qq.com>
Co-authored-by: Kimi Code <noreply@moonshot.cn>
Co-authored-by: zjy0516 <riverclouds.zhu@qq.com>
Co-authored-by: Codex <noreply@openai.com>
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2026-09-10 20:16:26 +08:00 |
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Li, Jiang
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c3ccc0e957
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[Model] Add DeepSeek-V4 CPU backend (#55355)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-09-10 14:14:48 +08:00 |
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Colin Z
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588a813a60
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[ROCm] [BugFix] Fix AITER MXFP4 ASM-GEMM crash on unfused shared experts (#55213)
Signed-off-by: Colin Zeng <Colin.Zeng@amd.com>
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2026-09-10 05:23:36 +00:00 |
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Michael LazosandOpenAI Codex
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28a73ccfba
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[Kernel] Add NVFP4 support to the torch linear backend (#53319)
Signed-off-by: Michael Lazos <mlazos@meta.com>
Co-authored-by: OpenAI Codex <codex@openai.com>
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2026-09-08 20:30:05 -04:00 |
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Roderick Wuandmgoin
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2c9d68f80b
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[Quant][Kernel] Remove GPTQ Group/Dynamic Activation Ordering (#54809)
Signed-off-by: Roderick-Wu <roderickwu2003@gmail.com>
Signed-off-by: Roderick Wu <roderickwu2003@gmail.com>
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: mgoin <mgoin64@gmail.com>
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2026-09-08 12:45:12 -07:00 |
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Stefano Castagnetta
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13cf9e05c1
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[Perf][Quant][NVFP4] Prefer W4A4 linear kernels over weight-only ones on SM120/121 (#55170)
Signed-off-by: Stefano Castagnetta <scastagnetta@nvidia.com>
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2026-09-08 15:06:45 +04:00 |
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1713b9866a
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[2/N][warmup][DSv4] Migrate sequence and DCP kernels (#53564)
Signed-off-by: LopezCastroRoberto <rocastro@redhat.com>
Co-authored-by: Codex <codex@openai.com>
Co-authored-by: OpenAI Codex <noreply@openai.com>
Co-authored-by: Lucas Wilkinson <LucasWilkinson@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-09-07 09:35:54 -04:00 |
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Jee Jee Li
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199cb9b964
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[Kernel] Remove unused fake implementation (#55535)
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
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2026-09-06 17:54:32 -07:00 |
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b7624069ff
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[Fusion] Manual ActivationQuantFusionPass initial application (#51415)
Signed-off-by: mgoin <mgoin64@gmail.com>
Signed-off-by: ElizaWszola <ewszola@redhat.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: ElizaWszola <ewszola@redhat.com>
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2026-09-03 13:37:31 -04:00 |
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ee3c00bbf4
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[Performance] Register Triton W4A16 GEMM as a custom op (#51453)
Signed-off-by: giuseppegrossi <ggrossi@amd.com>
Co-authored-by: TJian <tunjian.tan@embeddedllm.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
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2026-09-01 22:55:34 -05:00 |
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mingg26andOpenAI Codex
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259a209bfa
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[Kimi-K3][Perf] Prefetch ll_bf16 router weights for M=1 (#53524)
Signed-off-by: ming <ming@inferact.ai>
Co-authored-by: OpenAI Codex <codex@openai.com>
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2026-09-01 21:40:19 +00:00 |
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7a977c0699
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[ModelOpt] Redesign the LinearMethod classes using the generic QuantKey-driven method (#49381)
Signed-off-by: Juhi Mittal <juhim@nvidia.com>
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: mgoin <mgoin64@gmail.com>
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2026-09-01 16:28:56 -04:00 |
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Lain
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882ca8d696
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[Kernel] add Flashinfer cutedsl w4a16 linear (#53014)
Signed-off-by: Siyuan Fu <siyuanf@nvidia.com>
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2026-09-01 02:49:14 +00:00 |
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afriedriandAndreas Karatzas
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2f1cba799e
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[ROCm] remove VLLM_ROCM_USE_AITER_FP4_ASM_GEMM environment variable; make w4a4 use the preshuffle triton+asm by default (#53141)
Signed-off-by: Andy Friedrich <afriedri@amd.com>
Signed-off-by: afriedri <afriedri@amd.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
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2026-08-28 18:59:53 +00:00 |
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7c877062ac
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[kernel] Integrate FlashInfer BF16 CuTeDSL Low Latency GEMM (#50572)
Signed-off-by: jiahanc <173873397+jiahanc@users.noreply.github.com>
Co-authored-by: OpenAI Codex <codex@openai.com>
Co-authored-by: Jee Jee Li <pandaleefree@gmail.com>
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2026-08-27 22:29:12 +00:00 |
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SeonjinandMisha Goin
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bd8865a299
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[Kernel] Add FlashInfer TRTLLM MXFP8 linear backend (#52204)
Signed-off-by: seonjinn <sna@nvidia.com>
Signed-off-by: Misha Goin <mgoin64@gmail.com>
Co-authored-by: Misha Goin <mgoin64@gmail.com>
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2026-08-20 10:07:22 -04:00 |
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Shanshan Shen
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d626108b18
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[ROCm][Perf] Fuse DeepSeek-V4 mHC post/pre and RMSNorm with AITER (#52737)
Signed-off-by: shen-shanshan <467638484@qq.com>
Signed-off-by: Shanshan Shen <87969357+shen-shanshan@users.noreply.github.com>
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2026-08-20 04:51:04 +00:00 |
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Misha GoinandOpenAI Codex
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541c6d64c1
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[Bugfix][Quantization] Support CT block FP8 with Marlin (#52966)
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: OpenAI Codex <codex@openai.com>
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2026-08-19 12:41:26 -07:00 |
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