 Turner JabbourandClaude
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7aab6e2684
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[ROCm][Bugfix] Enable the fp32 head_dtype torch.mm fast path on ROCm (#48688)
Signed-off-by: Turner Jabbour <doubleujabbour@gmail.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-07-15 08:18:22 +00:00 |
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Giuseppe Grossi
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d119beb1b9
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[ROCm] Add tuned selective_state_update config for AMD MI350 (#48159)
Signed-off-by: Giuseppe Grossi <ggrossi@amd.com>
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2026-07-15 10:18:09 +03:00 |
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e281ac663a
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[Rust Frontend] Integrate MM audio support (#48554)
Co-authored-by: Isotr0py <Isotr0py@outlook.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Signed-off-by: Bugen Zhao <i@bugenzhao.com>
Signed-off-by: Isotr0py <Isotr0py@outlook.com>
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2026-07-15 15:00:17 +08:00 |
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Charlie FuandAndreas Karatzas
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adce068118
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[ROCm][CI] fix test_common.py (#48676)
Signed-off-by: charlifu <charlifu@amd.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
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2026-07-15 06:42:06 +00:00 |
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drakoshaandMatthew Bonanni
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6472131298
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[Bugfix] Set kv_quant_mode on the generic MLA KV-cache spec (#48379)
Signed-off-by: Mikhail Kostryukov <mike@triptrack.net>
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Co-authored-by: Matthew Bonanni <mbonanni@redhat.com>
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2026-07-15 03:36:52 +00:00 |
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Jee Jee Li
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fdf2cf66d3
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[LoRA][1/N] Integrate flashinfer MoE LoRA for BF16 model (#48632)
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
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2026-07-15 10:54:00 +08:00 |
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HDCharles
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9b2be4e9a5
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[Quant] Enable humming w[2-7]a[4,8] inference with compressed-tensors (#46390)
Signed-off-by: HDCharles <charlesdavidhernandez@gmail.com>
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2026-07-14 20:22:31 -06:00 |
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Andreas Karatzas
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3ad85e0de4
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[CI][AMD] Configure MI300 tests for native execution without DinD (#48387)
Signed-off-by: Andreas Karatzas <akaratza@amd.com>
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2026-07-15 02:14:16 +00:00 |
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gnovack
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f7aadae5e5
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add pad-aware reduce path (#48385)
Signed-off-by: gnovack <novackgm@gmail.com>
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2026-07-14 18:05:50 -07:00 |
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Wentao Yeandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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442c421e79
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[Perf] Remove redundant repeat and copy for dsv4, 1.8% E2E TPOT improvement. (#48137)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-07-15 00:48:10 +00:00 |
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JoanandDakai An
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0bd6b85a1f
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[Bugfix] Preserve unloaded non-persistent buffers during layerwise reload (#44371)
Signed-off-by: Joan Velja <joan.velja22@gmail.com>
Co-authored-by: Dakai An <77474977+andakai@users.noreply.github.com>
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2026-07-14 17:46:29 -07:00 |
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vanshbhatia-amdandvanshbhatia-amd
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7ffb98e248
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[ROCm] Retune MI355 selective_state_update float32 config on the unified effective_batch grid (#48373)
Signed-off-by: vanshbhatia-amd <210711135+vanshbhatia-amd@users.noreply.github.com>
Co-authored-by: vanshbhatia-amd <210711135+vanshbhatia-amd@users.noreply.github.com>
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2026-07-14 18:26:35 +00:00 |
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ca3618bc69
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[Doc] Sync four function docstrings with their signatures (#45437)
Signed-off-by: Daoyuan Li <94409450+DaoyuanLi2816@users.noreply.github.com>
Co-authored-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-07-14 13:10:13 -04:00 |
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Michael Goin
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b2f7d2560a
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[Bugfix] Make MLA+SWA check the layer's backend, not the model config (#48520)
Signed-off-by: mgoin <mgoin64@gmail.com>
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2026-07-14 09:53:34 -07:00 |
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Wentao Ye
|
1ff9429655
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[CI Bug] Fully solve accuracy issue for DSv3.2 + MTP + Sequence Parallel (#48036)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-07-14 10:00:24 -04:00 |
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karthik
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b6754f536e
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[Model] Enable LoRA support for tower and connector in LlavaNextVideo (#48594)
Signed-off-by: gangula-karthik <gkarthik923@gmail.com>
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2026-07-14 20:09:38 +08:00 |
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adsridharandBartosz Stefaniak
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894ebb27f5
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Add Cosmos3 Edge Reasoner model (#48291)
Signed-off-by: Bartosz Stefaniak <bstefaniak@nvidia.com>
Co-authored-by: Bartosz Stefaniak <bstefaniak@nvidia.com>
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2026-07-14 08:14:50 +00:00 |
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Roberto L. CastroandLucas Wilkinson
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0762f2afeb
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[Perf][Feat] Add generic cuteDSL LL BF16 router (GEMM) (#42562)
Signed-off-by: LopezCastroRoberto <rocastro@redhat.com>
Signed-off-by: Lucas Wilkinson <lwilkins@redhat.com>
Signed-off-by: Roberto L. Castro <38211239+LopezCastroRoberto@users.noreply.github.com>
Co-authored-by: Lucas Wilkinson <lwilkins@redhat.com>
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2026-07-13 23:01:21 -07:00 |
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vanshbhatia-amdandvanshbhatia-amd
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31be872f55
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[ROCm] Retune MI355 selective_state_update float16 config on the unified effective_batch grid (#48372)
Signed-off-by: vanshbhatia-amd <210711135+vanshbhatia-amd@users.noreply.github.com>
Co-authored-by: vanshbhatia-amd <210711135+vanshbhatia-amd@users.noreply.github.com>
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2026-07-14 05:16:29 +00:00 |
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nemanjaudovic
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dcf4072da9
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[Perf][ROCm] Fix GDN KKT warmup regression on RDNA by avoiding fp32 tl.dot (#45000)
Signed-off-by: Saeid Rostami <srostami@amd.com>
Signed-off-by: nemanjaudovic <nudovic@amd.com>
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2026-07-13 20:48:54 -07:00 |
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Matthias GehreandAndreas Karatzas
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382bbd5144
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[ROCm][Kernel] Add HybridW4A16LinearKernel: Triton prefill + HIP skinny decode (#40977)
Signed-off-by: Matthias Gehre <matthias.gehre@amd.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
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2026-07-13 20:22:00 -07:00 |
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akii96andPawel Kowalski
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b50ef9c6ed
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[ROCm][MiniMax-M2] Dispatch fused QK-norm + AllReduce via AITER (#44849)
Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
Co-authored-by: Pawel Kowalski <pawel.kowalski@amd.com>
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2026-07-14 03:10:16 +00:00 |
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Dan Blanaru
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9e289c553c
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up FI fp8 moe topk to 32 (#44462)
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2026-07-14 02:58:16 +00:00 |
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Matthew BonanniandClaude Opus 4.8
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c4f5cd60da
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[1/N] Add dense MHA path for sparse MLA short sequences (#47327)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
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2026-07-14 00:29:56 +00:00 |
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Zhenzhong XuandKunshang Ji
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0b0ef8d7eb
|
[Quantization][INC][ARK] Support INT2 XPU WOQ Linear (#47521)
Signed-off-by: Zhenzhong1 <zhenzhong.xu@intel.com>
Signed-off-by: Zhenzhong Xu <zhenzhong.xu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-07-14 08:29:45 +08:00 |
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gnovackandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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21472f32ea
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add pad-aware swiglu limit kernel (#48287)
Signed-off-by: gnovack <novackgm@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-07-13 16:48:19 -07:00 |
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Snehlata
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7738ef35b8
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[Feat] Add Support for BertForMaskedLM to vLLM (#48463)
Signed-off-by: atalhens <sneh.lata@nutanix.com>
|
2026-07-13 20:56:25 +00:00 |
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wenpengw-nvandRoger Wang
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9a21f0d1a3
|
[BugFix] Initialize model_config for Qwen3-VL MoE (#44863)
Signed-off-by: wenpengw-nv <wenpengw@nvidia.com>
Co-authored-by: Roger Wang <hey@rogerw.io>
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2026-07-13 13:43:53 -07:00 |
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shanjiaz
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7dc447dda7
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Added sliding window attention support for qwen-eagle3 architecture (#47568)
Signed-off-by: shanjiaz <zsjwpianpian@gmail.com>
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2026-07-13 20:20:44 +00:00 |
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stefankoncarevicandHarry Mellor
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9427c45386
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[ROCm][CI] Transformers: pass only one of input_ids/inputs_embeds (#48258)
Signed-off-by: Stefan Koncarevic <stefan.koncarevic@amd.com>
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Co-authored-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-07-13 17:28:50 +00:00 |
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Yan Ma
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c2c9f7c5e2
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remove force channels_last in Idefics3MultiModalProcessor (#48467)
Signed-off-by: Yan Ma <yan.ma@intel.com>
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2026-07-13 14:18:57 +00:00 |
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107a03ba63
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[Core] Support fp32 lm_head for generation models via head_dtype (RFC #48305 §3.6) (#48390)
Signed-off-by: Karthik Kothuri <karthikkothuri2009@gmail.com>
Signed-off-by: wang.yuqi <yuqi.wang@daocloud.io>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: wang.yuqi <yuqi.wang@daocloud.io>
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2026-07-13 16:43:34 +08:00 |
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bea70c7cfc
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[Attention] Make sliding-window support an explicit backend capability (#48011)
Signed-off-by: NickLucche <nicolo.lucchesi@mistral.ai>
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
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2026-07-13 01:07:56 -07:00 |
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Canlin Guo
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36484e464a
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[BugFix] Restore full tokens for Qwen MTP When MoE SP (#48429)
Signed-off-by: gcanlin <canlinguosdu@gmail.com>
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2026-07-13 13:29:41 +08:00 |
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Yejing Lai
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8c5dafcd09
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[Bugfix][UT]Fix EagleMiniCPMForCausalLM meet TypeError (#48452)
Signed-off-by: Lai, Yejing <yejing.lai@intel.com>
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2026-07-13 04:37:23 +00:00 |
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05fa8183a6
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[CPU][Spec Decode] Support DFlash speculative decoding for GDN models on CPU (#46090)
Signed-off-by: guybd <guy.boudoukh@intel.com>
Signed-off-by: Guy Boudoukh <guy.boudoukh@intel.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-07-13 04:16:18 +00:00 |
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zzt
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2595d5cebc
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[Model] Optimize Qwen3.5 on H20 (#48350)
Signed-off-by: zzt <zengzetang.zzt@antgroup.com>
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2026-07-13 03:30:48 +00:00 |
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Tanish MalekarandClaude Sonnet 4.6
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e26264f3ef
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[Kernel] Implement CUDA kernel for ReLUSquaredActivation (relu^2) (#39058)
Signed-off-by: Tanish Malekar <tanishmalekar32@gmail.com>
Co-authored-by: Claude Sonnet 4.6 <noreply@anthropic.com>
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2026-07-12 19:18:03 -07:00 |
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Canlin Guoandyewentao256
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a02984ed47
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[Perf][Qwen] Replace MOE all-reduce with reduce-scatter (#47006)
Signed-off-by: gcanlin <canlinguosdu@gmail.com>
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: yewentao256 <zhyanwentao@126.com>
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2026-07-12 06:14:49 +00:00 |
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19069bcbd5
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FP32 router GEMV optimization (#48335)
Signed-off-by: peiyuanz <peiyuanz@inferact.ai>
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
Co-authored-by: peiyuanz <peiyuanz@inferact.ai>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: zhouzhou <zhouzhou@zhouzhoudeMacBook-Pro.local>
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2026-07-11 13:07:48 +00:00 |
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Qiming ZhangandKunshang Ji
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0b6636cbcb
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[XPU]remove is_xxx from moe class and bump up kernels (#48079)
Signed-off-by: mayuyuace <qiming1.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-07-11 09:27:13 +00:00 |
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Harry Mellor
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4a6440acef
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Bump Transformers version to 5.13.0 (#47867)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-07-11 00:56:14 -07:00 |
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Jimmy Lee
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092387963c
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[BugFix] weights processing peak memory reduction for nvfp4 MoE layers (#46276)
Signed-off-by: Jimmy Lee <hirejimmylee@gmail.com>
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2026-07-11 02:05:35 +00:00 |
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Joe Rowellandmgoin
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1bf3997eae
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[Quantization] Bound peak memory when repacking FP4 MoE weights for Marlin (#47851)
Signed-off-by: Joe Rowell <joerowell4@gmail.com>
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: mgoin <mgoin64@gmail.com>
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2026-07-10 19:46:13 -06:00 |
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Michael GoinandClaude Fable 5
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29fd688892
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Add VLLM_FLASHINFER_AUTOTUNE_SKIP_OPS and skip CuTeDSL fp4_gemm autotuning by default (#48268)
Signed-off-by: mgoin <mgoin64@gmail.com>
Signed-off-by: Michael Goin <mgoin64@gmail.com>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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2026-07-10 18:13:08 -07:00 |
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Michael Goin
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08dfd68610
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[Model] Add LongCat-Flash-Lite (n-gram embedding) (#47857)
Signed-off-by: mgoin <mgoin64@gmail.com>
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2026-07-10 07:17:50 -07:00 |
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85c09e9885
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fix: correct load_weights track logic and enable weight integrity for… (#41811)
Signed-off-by: Yipeng Hu <i26268@metax-tech.com>
Signed-off-by: HuYiPeng <144002351+MynameFelix@users.noreply.github.com>
Signed-off-by: Isotr0py <Isotr0py@outlook.com>
Co-authored-by: Yipeng Hu <i26268@metax-tech.com>
Co-authored-by: Isotr0py <Isotr0py@outlook.com>
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2026-07-10 14:08:20 +00:00 |
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FAN YUCHEN
|
fabec87f63
|
[Model] Migrate MistralLarge3ForCausalLM to AutoWeightsLoader (#48153)
Signed-off-by: Yuchen Fan <functionhx@gmail.com>
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2026-07-10 12:27:58 +00:00 |
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Nick HillandClaude Opus 4.8
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7614b88ebd
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[Bugfix][Spec Decode] Fix DFlash draft/target layer-count mismatch (#48113)
Signed-off-by: Nick Hill <nickhill123@gmail.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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2026-07-10 04:42:53 -07:00 |
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Jiangyun Zhu
|
300e33797f
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[Perf] fuse more rmsnorm and all-reduce in qwen3.5 (#46998)
Signed-off-by: zjy0516 <riverclouds.zhu@qq.com>
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2026-07-10 15:37:51 +08:00 |
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