 Kunshang JiandJiang Li
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96b6f475dd
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Remove hardcoded device="cuda" to support more devices (#2503)
Co-authored-by: Jiang Li <jiang1.li@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2024-02-01 15:46:39 -08:00 |
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9090bf02e7
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Support FP8-E5M2 KV Cache (#2279)
Co-authored-by: zhaoyang <zhao.yang16@zte.com.cn>
Co-authored-by: Zhuohan Li <zhuohan123@gmail.com>
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2024-01-28 16:43:54 -08:00 |
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Hanzhi Zhou
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380170038e
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Implement custom all reduce kernels (#2192)
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2024-01-27 12:46:35 -08:00 |
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9b945daaf1
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[Experimental] Add multi-LoRA support (#1804)
Co-authored-by: Chen Shen <scv119@gmail.com>
Co-authored-by: Shreyas Krishnaswamy <shrekris@anyscale.com>
Co-authored-by: Avnish Narayan <avnish@anyscale.com>
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2024-01-23 15:26:37 -08:00 |
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Cade Daniel
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18bfcdd05c
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[Speculative decoding 2/9] Multi-step worker for draft model (#2424)
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2024-01-21 16:31:47 -08:00 |
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Zhuohan Li
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ef9b636e2d
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Simplify broadcast logic for control messages (#2501)
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2024-01-19 11:23:30 -08:00 |
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Woosuk Kwon
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35c4bc20d9
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[Minor] Fix err msg (#2431)
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2024-01-12 14:02:52 -08:00 |
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Ben
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cb7a1c1cbf
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Suggest using dtype=half when OOM.
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2024-01-12 12:33:29 -08:00 |
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Jiaxiang
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6549aef245
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[DOC] Add additional comments for LLMEngine and AsyncLLMEngine (#1011)
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2024-01-11 19:26:49 -08:00 |
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Zhuohan Li
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fd4ea8ef5c
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Use NCCL instead of ray for control-plane communication to remove serialization overhead (#2221)
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2024-01-03 11:30:22 -08:00 |
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Woosuk Kwon
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c3372e87be
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Remove dependency on CuPy (#2152)
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2023-12-17 01:49:07 -08:00 |
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Woosuk Kwon
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e1d5402238
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Fix all-reduce memory usage (#2151)
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2023-12-17 01:44:45 -08:00 |
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37ca558103
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Optimize model execution with CUDA graph (#1926)
Co-authored-by: Chen Shen <scv119@gmail.com>
Co-authored-by: Antoni Baum <antoni.baum@protonmail.com>
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2023-12-16 21:12:08 -08:00 |
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Woosuk Kwon
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30bad5c492
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Fix peak memory profiling (#2031)
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2023-12-12 22:01:53 -08:00 |
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Woosuk Kwon
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27feead2f8
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Refactor Worker & InputMetadata (#1843)
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2023-11-29 22:16:37 -08:00 |
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boydfdandran_lin
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4bb6b67188
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fix RAM OOM when load large models in tensor parallel mode. (#1395)
Co-authored-by: ran_lin <rlin@thoughtworks.com>
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2023-11-20 19:02:42 -08:00 |
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Simon Mo
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5ffc0d13a2
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Migrate linter from pylint to ruff (#1665)
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2023-11-20 11:58:01 -08:00 |
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Yanming W
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8efe23f150
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Fix input_metadata.selected_token_indices in worker prepare_inputs (#1546)
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2023-11-08 14:19:12 -08:00 |
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Antoni Baum
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9738b84a08
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Force paged attention v2 for long contexts (#1510)
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2023-11-01 16:24:32 -07:00 |
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Woosuk Kwon
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0ce8647dc5
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Fix integer overflows in attention & cache ops (#1514)
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2023-10-31 15:19:30 -07:00 |
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Antoni Baum
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15f5632365
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Delay GPU->CPU sync in sampling (#1337)
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2023-10-30 09:01:34 -07:00 |
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Woosuk Kwon
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c1376e0f82
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Change scheduler & input tensor shape (#1381)
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2023-10-16 17:48:42 -07:00 |
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Antoni Baum
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ee92b58b3a
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Move bfloat16 check to worker (#1259)
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2023-10-07 22:10:44 -07:00 |
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Woosuk Kwon
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2e8e49fce3
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[Fix] Remove false assertion (#1222)
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2023-09-28 10:52:38 -07:00 |
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Woosuk Kwon
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a8e98aee0c
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Fix Mistral model (#1220)
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2023-09-28 10:44:05 -07:00 |
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Chris Bamfordandtimlacroix
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bb1ba58f06
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[Mistral] Mistral-7B-v0.1 support (#1196)
Co-authored-by: timlacroix <t@mistral.ai>
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2023-09-28 10:41:03 -07:00 |
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Antoni Baum
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cf5cb1e33e
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Allocate more shared memory to attention kernel (#1154)
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2023-09-26 22:27:13 -07:00 |
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Woosuk Kwon
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2ac4d5e2bf
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Replace DtypeTensor (#1123)
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2023-09-21 00:51:47 -07:00 |
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Zhuohan Li
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002800f081
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Align vLLM's beam search implementation with HF generate (#857)
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2023-09-04 17:29:42 -07:00 |
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Zhuohan Li
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1b0bd0fe8a
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Add Falcon support (new) (#592)
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2023-08-02 14:04:39 -07:00 |
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Antoni Baum
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9925c17940
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Ray placement group support (#397)
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2023-07-19 22:49:31 -07:00 |
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Zhuohan Li
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d6fa1be3a8
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[Quality] Add code formatter and linter (#326)
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2023-07-03 11:31:55 -07:00 |
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Zhuohan Li
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0b7db411b5
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[Bug] Fix the OOM condition for CPU cache (#260)
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2023-06-26 11:16:13 -07:00 |
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Woosuk Kwon
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0b98ba15c7
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Change the name to vLLM (#150)
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2023-06-17 03:07:40 -07:00 |
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