 Tianmu LiandOpenAI Codex
|
c6c33f2b1f
|
[CPU] Support FP16/BF16 persisted GDN state on AMX (#52191)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: OpenAI Codex <noreply@openai.com>
|
2026-08-31 16:32:20 +08:00 |
|
|
Li, Jiang
|
fdbf2ddbd2
|
[Bugfix][CPU] Fix several bugs (#54042)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-08-31 15:33:06 +08:00 |
|
|
Li, Jiang
|
e4d61d0d22
|
[CPU] Add AMX-only high-performance MLA backend for DeepSeek V2/V3/R1 (#52616)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-08-19 10:28:52 +08:00 |
|
|
ccaadaroandLi, Jiang <jiang1.li@intel.com>
|
bda4c3e8ee
|
[CPU] Fold the MXFP4 block scale in 2 instructions instead of 4 (#51583)
Signed-off-by: ccaadaro <ccanadar@unex.es>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-08-14 08:19:21 +00:00 |
|
|
velonica0andLi, Jiang <jiang1.li@intel.com>
|
ac7509e2b1
|
[Bugfix][CPU][RISC-V] Fix build: make FP32Vec copy constructors non-explicit (#51099)
Signed-off-by: velonica0 <like@mail.nankai.edu.cn>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-08-14 04:59:01 +00:00 |
|
|
|
61826c1c6f
|
[Hardware][Power] Unqualized MoE Backend for Power (VSX) (#51624)
Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Antigravity <antigravity@google.com>
|
2026-08-13 10:56:09 +08:00 |
|
|
Rehan KhanandLi, Jiang <jiang1.li@intel.com>
|
b22afe45ac
|
[CPU] Enable GPTQ and AWQ quantization for s390x (#51148)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-08-10 11:41:43 +08:00 |
|
|
Tianmu Li
|
700d39b558
|
[CPU] Optimize routed FP8/MXFP4 MoE GEMM dispatch (#50949)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
|
2026-08-08 12:56:14 +08:00 |
|
|
Wentao Ye
|
c84789c40b
|
[Refactor] Remove kernel dead code (#51051)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
|
2026-08-07 01:20:19 -07:00 |
|
|
maobaolongandLi, Jiang <jiang1.li@intel.com>
|
13726c80fe
|
[CPU] Add MLA backend so DeepSeek-V2/V3 can run on CPU (#49453)
Signed-off-by: baoloongmao <baoloongmao@tencent.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-08-06 16:51:41 +08:00 |
|
|
Harjoth Khara
|
122b3d46b6
|
[Bugfix][CPU] Fix macOS build: std::sqrt is not constexpr under libc++ (#50915)
Signed-off-by: harjoth <harjoth.khara@gmail.com>
|
2026-08-04 14:56:33 +00:00 |
|
|
|
0a6446005d
|
[CPU] Migrate unquantized MoE to the modular-kernel experts structure (#50133)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Fadi Arafeh <fadi.arafeh@arm.com>
|
2026-08-03 14:55:04 +08:00 |
|
|
Rehan KhanandLi, Jiang <jiang1.li@intel.com>
|
88bc8fb56f
|
[CPU][s390x] Optimize inference perf and add oneDNN INT8 GEMM for s390x (#50219)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-07-31 17:49:31 +08:00 |
|
|
Li, JiangandClaude
|
072a472782
|
[CPU] Bump up CPU kernels to latest version (#50387)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Co-authored-by: Claude <noreply@anthropic.com>
|
2026-07-30 19:18:43 +08:00 |
|
|
|
65a1a16594
|
[CPU] Fix FP8 attention scratchpad sizing (#50194)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: Codex <noreply@openai.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-07-29 15:34:37 +08:00 |
|
|
Rehan KhanandLi, Jiang <jiang1.li@intel.com>
|
db7a79cbf7
|
[CPU] Fix s390x builds and update torch version in dockerfile (#50144)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-07-29 12:52:17 +08:00 |
|
|
|
544cb724c8
|
[CPU][Spec Decode] Optimize GDN conv path for speculative decoding (#48577)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: Codex <codex@openai.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-07-27 06:20:14 +00:00 |
|
|
Fadi ArafehandLi, Jiang <jiang1.li@intel.com>
|
c314af1abf
|
[CPU][Perf] INT8 Fused MoE Kernel for Arm CPUs (#48637)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-07-27 05:53:09 +00:00 |
|
|
Akash kaothalkarandAkash kaothalkar
|
f19ee27e39
|
[Hardware][Power] Add FAST_EXP for Power (#49571)
Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
|
2026-07-27 05:47:29 +00:00 |
|
|
SyaandLi, Jiang <jiang1.li@intel.com>
|
5b3762a7f0
|
[Bugfix][CPU] Fix Clang OpenMP build on macOS (#49021)
Signed-off-by: markyangcc <mmdou3@163.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-07-21 09:58:52 +00:00 |
|
|
|
5c9f6557d7
|
[Hardware][CPU] Enable granite-4 model on cpu (#47641)
Signed-off-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com>
Signed-off-by: Akash Kaothalkar <akashkaothalkar@dhcp-9-123-5-76.bl1-in.ibm.com>
Signed-off-by: Akash Kaothalkar <akashkaothalkar@Akashs-MBP.lan>
Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Akash Kaothalkar <akashkaothalkar@dhcp-9-123-5-76.bl1-in.ibm.com>
Co-authored-by: Akash Kaothalkar <akashkaothalkar@Akashs-MBP.lan>
Co-authored-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com>
Co-authored-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-07-20 06:15:16 +00:00 |
|
|
Michael Goin
|
0b54201a04
|
[CI] Build macOS arm64 CPU wheel natively on the macmini queue (#48289)
Signed-off-by: mgoin <mgoin64@gmail.com>
|
2026-07-14 19:40:26 +00:00 |
|
|
|
05fa8183a6
|
[CPU][Spec Decode] Support DFlash speculative decoding for GDN models on CPU (#46090)
Signed-off-by: guybd <guy.boudoukh@intel.com>
Signed-off-by: Guy Boudoukh <guy.boudoukh@intel.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-07-13 04:16:18 +00:00 |
|
|
|
c85d72076a
|
[HARDWARE][POWER] optimize math functions of VSX power (#47321)
Signed-off-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com>
Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com>
Co-authored-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com>
Co-authored-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
|
2026-07-07 09:35:47 +00:00 |
|
|
Li, Jiang
|
344609ab17
|
[CI/Build] Fix pre-commit check (#47695)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-07-06 08:24:24 +00:00 |
|
|
velonica0
|
990c2a0187
|
[RISC-V] Enable BF16 on VLEN=256 hardware (#45243)
Signed-off-by: velonica0 <like@mail.nankai.edu.cn>
|
2026-07-06 06:05:16 +00:00 |
|
|
LiuTongandClaude
|
e433634c78
|
[Performance][Hardware][RISC-V] Reduce LMUL pressure in INT4 LUT dequant (#47538)
Signed-off-by: liutong <liutong@iscas.ac.cn>
Co-authored-by: Claude <noreply@anthropic.com>
|
2026-07-06 05:58:56 +00:00 |
|
|
LiuTongandClaude
|
16f8110935
|
[Bugfix][CPU][RISC-V] Fix VLEN detection for RVV attention path (#47532)
Signed-off-by: liutong <liutong@iscas.ac.cn>
Co-authored-by: Claude <noreply@anthropic.com>
|
2026-07-06 05:58:03 +00:00 |
|
|
Fadi Arafeh
|
f1073c050c
|
[CPU][BugFix] Multiple fixes to w4a8_int8 CPU MoE path (#46739)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
|
2026-07-06 05:39:20 +00:00 |
|
|
gausah01
|
26eb87204d
|
[Bugfix] Fix CPU split-KV scratchpad sizing (#45844)
Signed-off-by: Gauri Sahnan <gauri.sahnan@arm.com>
|
2026-07-04 06:47:23 +00:00 |
|
|
almayneandLi, Jiang <jiang1.li@intel.com>
|
89e99202f2
|
[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639)
Signed-off-by: Anna Mayne <anna.mayne@arm.com>
Signed-off-by: almayne <anna.mayne@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-06-30 23:24:40 -07:00 |
|
|
Michael GoinandClaude Opus 4.8
|
c6554f321c
|
[CPU] Fix macOS/Apple Silicon hang by enabling OpenMP in the build (#46769)
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
|
2026-06-26 14:32:21 -04:00 |
|
|
|
638b1a99cc
|
[CPU][RISC-V] Add RVV path for W4A8 INT4 GEMM (#45269)
Signed-off-by: wcy <233313160abc@gmail.com>
Co-authored-by: lyd1992 <liuyudong@iscas.ac.cn>
Co-authored-by: OpenAI Codex <codex@openai.com>
|
2026-06-25 08:18:10 +00:00 |
|
|
guybdandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
2396d91e93
|
[CPU][Spec Decode] Enable DFlash SD for CPU (#44029)
Signed-off-by: guybd <guy.boudoukh@intel.com>
Signed-off-by: Guy Boudoukh <guy.boudoukh@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
2026-06-25 15:32:48 +08:00 |
|
|
|
1aad125815
|
[CPU] Enable chunked prefill and prefix caching for qwen3.5 (#46202)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply@anthropic.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-06-25 03:49:21 +00:00 |
|
|
Fadi Arafeh
|
061043eaca
|
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
|
2026-06-24 14:14:35 +00:00 |
|
|
Rukhaiya2004
|
9f5117820f
|
[HARDWARE][POWER] Enable fp16 support for PowerPC (#46135)
Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com>
|
2026-06-23 13:24:49 +00:00 |
|
|
wcyandLi, Jiang <jiang1.li@intel.com>
|
d2c671c29b
|
[CPU][RISC-V] Add RVV micro GEMM for WNA16 (#44324)
Signed-off-by: wcy <233313160abc@gmail.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-06-22 12:53:54 +00:00 |
|
|
lyd1992andYuanSheng
|
021cdf72bc
|
Fix _riscv_supports_rvv_vlen128() to detect RVV on hardware without zvl flags (#43179)
Signed-off-by: liuyudong <liuyudong@iscas.ac.cn>
Co-authored-by: YuanSheng <yuansheng@isrc.iscas.ac.cn>
|
2026-06-18 21:22:35 +08:00 |
|
|
arghyadeep sarkar
|
93bbe94d3a
|
[Kernel] Add weightless RMSNorm CUDA kernels for has_weight=False (#41430) (#44109)
Signed-off-by: hello-args <args.sarkar@gmail.com>
|
2026-06-16 23:45:55 -07:00 |
|
|
Li, Jiang
|
a7fdfeef72
|
[CPU] Support Gemma Diffusion (#45690)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-06-16 14:39:56 +08:00 |
|
|
Li, Jiang
|
8760f972ca
|
[CPU] Refine CPU attention frontend (#45391)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-06-14 19:26:54 -07:00 |
|
|
wcyandlyd1992
|
f06aefb4e3
|
[CPU] Add missing scalar fallback for CPU W4A8 INT4 GEMM (#44523)
Signed-off-by: wcy <233313160abc@gmail.com>
Co-authored-by: lyd1992 <liuyudong@iscas.ac.cn>
|
2026-06-11 08:52:01 +00:00 |
|
|
Yuanyuan ChenandLi, Jiang <jiang1.li@intel.com>
|
0b995f8609
|
Use std::bit_cast for type punning in CPU kernels (#45089)
Signed-off-by: Yuanyuan Chen <cyyever@outlook.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-06-10 22:07:44 -07:00 |
|
|
velonica0
|
f31bc2ea60
|
[CPU][RISC-V] Enable oneDNN W8A8 INT8 to run on RISC-V (#44478)
Signed-off-by: velonica0 <like@mail.nankai.edu.cn>
|
2026-06-11 04:09:05 +00:00 |
|
|
SeongJun Leeandlesj0610
|
3099de3617
|
[Kernel][MoE] Add GELU_TANH to CPU, CUTLASS, and WNA16 MoE backends (#42027)
Signed-off-by: lesj0610 <lesj0610@users.noreply.github.com>
Co-authored-by: lesj0610 <lesj0610@users.noreply.github.com>
|
2026-06-02 17:12:08 -04:00 |
|
|
|
689b0eeb9e
|
[HARDWARE][POWER] Enable SHM communicator support for PowerPC (#43754)
Signed-off-by: Rukhaiya <rukhaiya@c643n08aix1-lp1.pok.stglabs.ibm.com>
Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com>
Co-authored-by: Rukhaiya <rukhaiya@c643n08aix1-lp1.pok.stglabs.ibm.com>
Co-authored-by: Akash kaothalkar <61960177+Akashcodes732@users.noreply.github.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-06-02 18:06:32 +08:00 |
|
|
Fadi ArafehandLi, Jiang <jiang1.li@intel.com>
|
0b25cf4419
|
[CPU][Perf] Enable fused kernels for GDN's gated delta rules (#43534)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-06-02 08:00:48 +00:00 |
|
|
wcyandLi, Jiang <jiang1.li@intel.com>
|
98f1279815
|
[CPU][RISC-V] Add missing RVV cpu_types helpers for WNA16 (#42730)
Signed-off-by: wcy <233313160abc@gmail.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-06-01 14:56:41 +08:00 |
|
|
zhao, zhenhui
|
771e1e48b1
|
[CPU] Enable non-divisible GQA for decode workitems in mixed batches (#43032)
Signed-off-by: zhejiangxiaomai <zhenhui.zhao@intel.com>
|
2026-05-26 14:15:47 +08:00 |
|