 ccaadaroandLi, Jiang <jiang1.li@intel.com>
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bda4c3e8ee
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[CPU] Fold the MXFP4 block scale in 2 instructions instead of 4 (#51583)
Signed-off-by: ccaadaro <ccanadar@unex.es>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-08-14 08:19:21 +00:00 |
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Tianmu Li
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700d39b558
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[CPU] Optimize routed FP8/MXFP4 MoE GEMM dispatch (#50949)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
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2026-08-08 12:56:14 +08:00 |
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Yuwen Zhou
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58d6a6e60a
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[CPU] Support cpu compressed-tensor w8a8 int8 moe (#42920)
Signed-off-by: yuwenzho <yuwen.zhou@intel.com>
Signed-off-by: Yuwen Zhou <yuwen.zhou@intel.com>
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2026-06-29 03:04:05 +00:00 |
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Yuwen Zhou
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0cd9b7af25
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[CPU] Support CPU W4A16 INT4 MoE (#43409)
Signed-off-by: yuwenzho <yuwen.zhou@intel.com>
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2026-06-12 07:12:37 +00:00 |
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Yuwen Zhou
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88a860d754
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[CPU] Add MXFP4 W4A16 MoE support (#41922)
Signed-off-by: yuwenzho <yuwen.zhou@intel.com>
Signed-off-by: Yuwen Zhou <yuwen.zhou@intel.com>
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2026-05-18 03:04:45 -07:00 |
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