 Nick Hill
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c28feab989
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[Core][MRV2] Freeze gc during V2 CG capture; skip per-descriptor cleanup (#54646)
Signed-off-by: Nick Hill <nickhill123@gmail.com>
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2026-08-31 19:37:46 -07:00 |
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Nick Hill
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4aab2b0ebe
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[Model Runner V2] Use MRV2 for all models by default (#53183)
Signed-off-by: Nick Hill <nickhill123@gmail.com>
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2026-08-27 11:59:34 -07:00 |
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Jee Jee Li
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88e1b11313
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[Perf] Tune FlashInfer all-reduce thresholds for single-node TP8 on SM103 (#53606)
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
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2026-08-26 01:46:56 +00:00 |
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Khushali Desai
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23ab0cfdbc
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speculative decoding under tensor parallelism (TP>1) , workspace creation select max hidden dim of target and draft model (#52193)
Signed-off-by: khushali9 <khushali.desai9@gmail.com>
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2026-08-24 21:33:36 +00:00 |
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Wentao Ye
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811d12ee26
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[Mypy Fix] Mypy fix for "vllm/model_executor/models/[eE][fF]" (#53381)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-08-22 15:41:27 -04:00 |
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Lucas Wilkinson
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8bdc70ec7b
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[6/N][KV-Cache Layout Refactor] Standardize KV cache layout (#51718)
Signed-off-by: Lucas Wilkinson <lwilkins@redhat.com>
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2026-08-21 17:47:49 -07:00 |
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Kevin H. Luu
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c0ff33404b
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Revert compile-cache device index regression on CPU (#53304)
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2026-08-21 16:08:13 -04:00 |
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Frederik Gossen
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47cd1c8885
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[Core] Add dynamo_timed tracing for print_readable (#40834)
Signed-off-by: Frederik Gossen <frgossen@meta.com>
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2026-08-21 09:07:21 -07:00 |
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Neil SchemenauerandTyler Michael Smith
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6dcc5d7cae
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[Bugfix] Include device index in compile cache paths (#38962)
Signed-off-by: Neil Schemenauer <nas@arctrix.com>
Signed-off-by: Tyler Michael Smith <tlrmchlsmth@gmail.com>
Co-authored-by: Tyler Michael Smith <tlrmchlsmth@gmail.com>
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2026-08-21 09:07:16 -07:00 |
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shanjiaz
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e078a2238a
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[Bugfix] Widen flashinfer.comm import guard so a failed import doesn't abort engine startup (#52241)
Signed-off-by: shanjiaz <zsjwpianpian@gmail.com>
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2026-08-14 16:27:24 +00:00 |
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Andreas Karatzas
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7e724dca89
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[ROCm] Fix AITER all-reduce fusion coverage (#50802)
Signed-off-by: Andreas Karatzas <akaratza@amd.com>
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2026-08-06 14:52:23 +08:00 |
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Rohan PotdarandClaude Opus 4.8
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d0ce3dadb6
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[ROCm]: Bump torch 2.12, triton 3.7, torchaudio, torchvision (#50607)
Signed-off-by: Rohan Potdar <rohan.potdar@amd.com>
Signed-off-by: Rohan138 <rohanpotdar138@gmail.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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2026-08-04 20:14:11 -05:00 |
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skysnow2001andDouglas Lehr
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f43e1d26e3
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[ROCm] Enable AITER and FP8 inference on GFX120x (#43615)
Signed-off-by: skysnow2001 <skysnow9285@gmail.com>
Co-authored-by: Douglas Lehr <91553416+dllehr-amd@users.noreply.github.com>
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2026-08-03 16:45:37 -05:00 |
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Wentao Ye
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0cf49a5d15
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[Refactor] Remove multiple dead codes (#50285)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-08-03 10:59:08 -04:00 |
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Richard ZouandCodex
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c27b080d26
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[compile] Fix fake kernel return dtype (#50444)
Signed-off-by: Richard Zou <zou3519@gmail.com>
Co-authored-by: Codex <noreply@openai.com>
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2026-07-30 19:50:02 +00:00 |
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BadrBasowid
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59e831c09a
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[Compilation]Fuse Transformers Residual Add + RMSNorm (#48757)
Signed-off-by: BadrBasowid <badr.basowid@gmail.com>
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2026-07-30 13:46:36 +00:00 |
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5fa0154448
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[Rubin] Enable NVLink all-reduce paths on SM107 (#49647)
Signed-off-by: Zachary Aristei <zaristei@nvidia.com>
Co-authored-by: Sahithi Chigurupati <chigurupati.sahithi@gmail.com>
Co-authored-by: hlu1 <14827759+hlu1@users.noreply.github.com>
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2026-07-29 20:53:25 +00:00 |
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afriedri
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f472ab0a4c
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Remove triton per group quant [ROCm] [Bugfix] (#49621)
Signed-off-by: Andy Friedrich <afriedri@amd.com>
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2026-07-28 05:53:46 +00:00 |
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Chaojun ZhangandKunshang Ji
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bf4f633b4c
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[XPU] Enable QK Norm + RoPE fusion pass on XPU (#49394)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-07-27 03:22:29 +00:00 |
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Schwinn Saereesitthipitak
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b5b61c622c
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[Core][Distributed] Add process-checkpoint lifecycle hooks for communicators (starting with Flashinfer) (#46877)
Signed-off-by: Schwinn Saereesitthipitak <schwinns@nvidia.com>
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2026-07-26 14:47:50 -04:00 |
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Woosuk Kwon
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213f681f81
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Revert "[Perf][GLM-5.2] Blackwell decode optimizations" (#49768)
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2026-07-24 16:04:59 -07:00 |
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dd72658e7d
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[Perf][GLM-5.2] Blackwell decode optimizations (#48597)
Signed-off-by: Peiyuan Zhou <peiyuanzhou1994@gmail.com>
Signed-off-by: zhou <zhou@zhoudeMacBook-Pro.local>
Signed-off-by: Stefan Koncarevic <stefan.koncarevic@amd.com>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: Giancarlo Delfin <32987265+TheEpicDolphin@users.noreply.github.com>
Co-authored-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: OpenAI Codex <codex@openai.com>
Co-authored-by: zhou <zhou@zhoudeMacBook-Pro.local>
Co-authored-by: stefankoncarevic <Stefan.Koncarevic@amd.com>
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2026-07-23 21:36:27 -07:00 |
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stefankoncarevicandAndreas Karatzas
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387189c429
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[ROCm] Remove redundant AITER fused_qk_rmsnorm probe (avoids config-time HIP init) (#47992)
Signed-off-by: Stefan Koncarevic <stefan.koncarevic@amd.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
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2026-07-21 22:58:14 -05:00 |
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Jack HuandDouglas Lehr
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2cab53ddee
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[Model][Hardware][AMD]: Part 1/2 -> Enable e2e QK Norm + RoPE + KV Cache runtime fusion for Qwen3-30B-A3B on ROCM_AITER_FA, and ROCM_AITER_UNIFIED_ATTN (#42749)
Signed-off-by: Jack Hu <Jack.Hu@amd.com>
Co-authored-by: Douglas Lehr <91553416+dllehr-amd@users.noreply.github.com>
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2026-07-16 17:39:04 -05:00 |
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Wentao Ye
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626c90b2d5
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[Refactor] Move fla to third party (#48500)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-07-16 19:22:36 +01:00 |
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nemanjaudovic
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81e13a0591
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[Compilation] Skip x.size(dim) in _decompose_size_nodes (#42543)
Signed-off-by: nemanjaudovic <nudovic@amd.com>
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2026-07-15 17:59:14 -07:00 |
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aoshen02andOpenAI Codex
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3b39fd284a
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[Bugfix][Spec Decode] Support heterogeneous QK fusion geometry (#48671)
Signed-off-by: aoshen02 <aoshen@inferact.ai>
Co-authored-by: OpenAI Codex <codex@openai.com>
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2026-07-14 22:37:10 -07:00 |
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emricksini-handSimon Mo
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fec64fea75
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[BugFix] Correct OTEL span start time for Dynamo compilation (#40698)
Signed-off-by: emricksini-h <emrick.birivoutin@hcompany.ai>
Co-authored-by: Simon Mo <simon.mo@hey.com>
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2026-07-13 16:25:03 -07:00 |
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Mohammad Miadh Angkad
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75fe92a316
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[Distributed][Perf] Enable FlashInfer MNNVL allreduce RMS quant fusion (#48064)
Signed-off-by: Mohammad Miadh Angkad <176301910+mmangkad@users.noreply.github.com>
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2026-07-13 15:02:59 +08:00 |
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Hugo Centeno
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5f8e73cb8b
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[Bugfix] Guard mixed-dtype allreduce RMSNorm quant fusions (#48330)
Signed-off-by: hcenteno <hugo.centeno@estudiantat.upc.edu>
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2026-07-12 09:39:27 +00:00 |
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429f405748
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[Bugfix] Guard CUDA-only rms_norm_per_block_quant in FUSED_OPS for non-CUDA builds (#47296)
Signed-off-by: Tsvika Shapira <tsvika@moonmath.ai>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-07-09 10:10:53 -04:00 |
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jescoandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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598d51153a
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[Bugfix][Distributed] Delegate MNNVL allreduce one-shot selection (#47589)
Signed-off-by: jesco-absolut <team@srswti.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-07-06 07:47:06 -07:00 |
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BadrBasowid
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740f379fae
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[ROCm][AITER] Directly Implement AITER Custom All-reduce in CudaCommunicator (#46065)
Signed-off-by: BadrBasowid <badr.basowid@gmail.com>
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2026-07-06 12:16:32 +00:00 |
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xaguilar-amd
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09663abde0
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[ROCm][MLA] Fuse MLA q/kv RMSNorm + FP8 per-token quant in the FP8 attention path (#44977)
Signed-off-by: Xavier Aguilar <xavier.aguilarfruto@amd.com>
Signed-off-by: Xavier Aguilar <Xavier.AguilarFruto@amd.com>
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2026-07-02 13:00:41 +08:00 |
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Yejing LaiandKunshang Ji
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f651a8a9a4
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[XPU][UT]Enable ut qk_norm_rope_fusion (#42486)
Signed-off-by: Lai, Yejing <yejing.lai@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-07-01 07:38:03 +00:00 |
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Nick Hill
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4e07ca2c92
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[Core] Add VLLM_GPU_SYNC_CHECK env var (#44800)
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2026-06-26 08:24:33 -07:00 |
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Jeff (Junze) Maandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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fc61c6fc26
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[Perf] Enable + tune FlashInfer fused allreduce at world_size=16 on SM 10.3 (GB300) (#46392)
Signed-off-by: Jeff Ma <jeffjma@umich.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-24 23:04:17 -07:00 |
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Mohammad Miadh Angkad
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d1a38c2762
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[Kernel][Performance] Add FlashInfer cutedsl NVFP4 GEMM backend (#42235)
Signed-off-by: Mohammad Miadh Angkad <176301910+mmangkad@users.noreply.github.com>
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2026-06-22 16:17:18 -04:00 |
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Tyler Michael SmithandClaude Opus 4.6
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e9de72fe6c
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[Bugfix] Guard model_config access in _log_compilation_config (#46198)
Signed-off-by: Tyler Michael Smith <tlrmchlsmth@gmail.com>
Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
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2026-06-20 19:26:38 +00:00 |
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Ace Eldeib
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b4092176b9
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[Bugfix] Complete one-shot fused all-reduce PDL at end to avoid NaN (#45448)
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2026-06-18 00:54:39 +00:00 |
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Ting SUNandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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7b5d60cc37
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[Bugfix][V1] Clean up compiled-model bytecode hooks on VllmRunner exit (#45195)
Signed-off-by: Ting Sun <suntcrick@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-16 20:31:17 -07:00 |
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Thomas Parnell
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ebf3a6d705
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[Bugfix] Fix trtllm fused allreduce+rms_norm for transformers backend (#45307)
Signed-off-by: Thomas Parnell <tpa@zurich.ibm.com>
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2026-06-16 08:34:27 +00:00 |
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Chaojun Zhang
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2725c84aae
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[XPU] Enable sequence parallel support for XPU (#38608)
Signed-off-by: chaojun-zhang <chaojun.zhang@intel.com>
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>
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2026-06-14 19:26:46 -07:00 |
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Markus HartikainenandFrida Andersson
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80e2c4462d
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[ROCm][Compile] Fuse AR + RMSNorm + per-group FP8 quant (+ DSv3.2 indexer fan-out) (#42864)
Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com>
Co-authored-by: Frida Andersson <fanderss@amd.com>
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2026-06-09 12:06:56 +00:00 |
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Vadim Gimpelson
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67d3792d99
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[Bugfix] Fix Qwen3.5-FP8 nightly fail. Guard fused_add_rms_norm input/weight dtype mismatch in RMSNorm + quant fusion (#44694)
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2026-06-06 08:46:14 -04:00 |
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Mike GandMichael Gschwind
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2f27c9a150
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Preserve layout-changing clones (#44574)
Signed-off-by: Michael Gschwind <mgschwind@nvidia.com>
Co-authored-by: Michael Gschwind <mgschwind@nvidia.com>
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2026-06-05 20:45:24 -04:00 |
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akii96andmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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4200f62147
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[ROCm][GPT-OSS] Fuse RoPE + static Q FP8 quant on fused RoPE+KV path (#42832)
Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-05 16:22:19 -05:00 |
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Harry Mellor
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a80af24356
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Speed up docs build (#44635)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-06-05 14:51:44 +00:00 |
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QiliangCui2023
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9354fb1ba5
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[Bugfix][Compile] Guard per_token_group_fp8_quant lookup on non-CUDA platforms (#44476)
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2026-06-04 09:31:50 -04:00 |
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d0975a4b50
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[perf] Add gemma RMS AR fusion (#42646)
Signed-off-by: jiahanc <173873397+jiahanc@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: Jiangyun Zhu <riverclouds.zhu@qq.com>
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2026-06-04 01:33:59 -07:00 |
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