 Jiangyun Zhu
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98ed0856f3
|
[Model] add GLM-5.3-Flash support (#53906)
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2026-09-03 09:40:35 -07:00 |
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Luyi XiaoandOpenAI Codex
|
aa71f9bcc4
|
[Bugfix] Log platform plugin detection failures (#52285)
Signed-off-by: Luyi Xiao <xiao.luy@northeastern.edu>
Co-authored-by: OpenAI Codex <codex@openai.com>
|
2026-09-01 19:11:52 +00:00 |
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|
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dbb7fffddb
|
[ROCm][MLA][DCP] Support causal multi-token verification (#51705)
Signed-off-by: Yichao Zhu <Yichao.Zhu@amd.com>
Signed-off-by: billishyahao <bill.he@amd.com>
Co-authored-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: billishyahao <bill.he@amd.com>
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2026-08-31 10:42:28 -07:00 |
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Tianmu LiandOpenAI Codex
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c6c33f2b1f
|
[CPU] Support FP16/BF16 persisted GDN state on AMX (#52191)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: OpenAI Codex <noreply@openai.com>
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2026-08-31 16:32:20 +08:00 |
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+5
|
e126687a9a
|
[Model] Support Qwen3.8-Flash-Next (#53896)
Signed-off-by: huanghaoyan.hhy <huanghaoyan.hhy@alibaba-inc.com>
Signed-off-by: andyluo7 <andy.luo@amd.com>
Signed-off-by: lishunyang12 <lishunyang03@gmail.com>
Signed-off-by: Harry Huang <huanghaoyan.hhy@alibaba-inc.com>
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Signed-off-by: Isotr0py <Isotr0py@outlook.com>
Signed-off-by: Lucas Wilkinson <lwilkins@redhat.com>
Signed-off-by: Yifan Qiao <yifanqiao@inferact.ai>
Signed-off-by: zjy0516 <riverclouds.zhu@qq.com>
Co-authored-by: zjy0516 <riverclouds.zhu@qq.com>
Co-authored-by: KungYork <firelikest@163.com>
Co-authored-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Yifan Qiao <yifanqiao@inferact.ai>
Co-authored-by: andyluo7 <43718156+andyluo7@users.noreply.github.com>
Co-authored-by: Isotr0py <mozf@inferact.ai>
Co-authored-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: OpenAI Codex <noreply@openai.com>
Co-authored-by: lishunyang12 <lishunyang03@gmail.com>
Co-authored-by: Vadim Gimpelson <156319763+vadiklyutiy@users.noreply.github.com>
Co-authored-by: Isotr0py <Isotr0py@outlook.com>
Co-authored-by: Lucas Wilkinson <lwilkins@redhat.com>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
Co-authored-by: OpenAI Codex <codex@openai.com>
|
2026-08-31 05:57:56 +00:00 |
|
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Yizhou
|
1ebff996a1
|
[Fix] Improve ROCm detection in WSL environments (#38434)
Signed-off-by: Yizhou Liu <liu_yizhou@outlook.com>
|
2026-08-30 04:23:10 +00:00 |
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Eoin-HoustounandClaude Fable 5
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30e2394c83
|
[Bugfix] Record non-ImportError attention backend probe failures instead of crashing engine init (#51703)
Signed-off-by: Eoin <eoin@turintech.ai>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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2026-08-20 02:36:00 -07:00 |
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Roger Wang
|
755492e37d
|
Revert "[Kernel] Gemma-4 FA4 FP8 Kernel" (#52987)
|
2026-08-19 10:48:46 -07:00 |
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Misha GoinandOpenAI Codex
|
f76d71d7ce
|
[CI/Build] Fix CPU platform pre-commit formatting (#52981)
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: OpenAI Codex <codex@openai.com>
|
2026-08-19 10:32:37 -07:00 |
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Dinesh Chitlangia
|
525b7bbb3a
|
[Bugfix][CPU] Enable C++ causal_conv1d GDN path and float32 SSM cache on non-AMX AVX-512BF16 CPUs (#49688)
Signed-off-by: Dinesh Chitlangia <dineshchitlangia@gmail.com>
|
2026-08-19 10:50:59 -05:00 |
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Li, Jiang
|
e4d61d0d22
|
[CPU] Add AMX-only high-performance MLA backend for DeepSeek V2/V3/R1 (#52616)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-08-19 10:28:52 +08:00 |
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Taneem Ibrahim
|
be3f614ff1
|
[CI] Register CPU CI "VLLM_CPU_CI_ENV" environment variable (#52633)
Signed-off-by: Taneem Ibrahim <taneem.ibrahim@gmail.com>
|
2026-08-18 08:28:00 -04:00 |
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Andreas Karatzas
|
44fc57d7b7
|
[ROCm][CI] Select CPU platform for native no-GPU jobs (#49515)
Signed-off-by: Andreas Karatzas <Andreas.Karatzas@amd.com>
|
2026-08-14 23:30:56 -07:00 |
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Lucas WilkinsonandClaude
|
57bd0ed441
|
[5/N][KV-Cache Layout Refactor] Backend-published KV packing via customize_spec (#51704)
Signed-off-by: Lucas Wilkinson <lwilkins@redhat.com>
Co-authored-by: Claude <noreply@anthropic.com>
|
2026-08-14 09:47:55 -04:00 |
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827a2af806
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[Kernel] Gemma-4 FA4 FP8 Kernel (#48666)
Signed-off-by: Qixiang Lin <qixiangl@nvidia.com>
Signed-off-by: Jhao-Ting Chen <jhaotingc@nvidia.com>
Co-authored-by: Qixiang Lin <qixiangl@nvidia.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: Yongye Zhu <zyy1102000@gmail.com>
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2026-08-13 17:42:00 -07:00 |
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wangxiyuan
|
73b83949f7
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[Platform] Add check_runner_kv_caches_multi_layer (#51633)
Signed-off-by: wangxiyuan <wangxiyuan1007@gmail.com>
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2026-08-13 19:25:07 +00:00 |
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PikaPikachu
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466855a2bf
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[ROCm] Enable DeepSeek-V4 on gfx11 (#47017)
This PR enables DeepSeek-V4 checkpoints on ROCm gfx11/RDNA devices.
Signed-off-by: Letian Kang <Letian.Kang@amd.com>
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2026-08-12 08:55:10 +08:00 |
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5426311d91
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[Kernel][ROCm][Perf] FlyDSL decode-attention kernel for 4-bit TurboQuant KV cache (#47896)
Signed-off-by: root <root@smci355-ccs-aus-m02-09.cs-aus.dcgpu>
Co-authored-by: root <root@smci355-ccs-aus-m02-09.cs-aus.dcgpu>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-08-11 08:45:39 -07:00 |
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Chaojun Zhang
|
f863387250
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[XPU] Fix UVA weight offloading (non-pinned-tensor views and static Triton launcher) (#51770)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
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2026-08-11 21:48:44 +08:00 |
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Kush Zingade
|
78e7fdd1ab
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[Bugfix][CPU] Make the Apple Silicon BF16 probe fall back instead of raising (#51627)
Signed-off-by: Kush Zingade <kush.zingade@gmail.com>
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2026-08-11 21:35:07 +08:00 |
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Isotr0py
|
073c510c91
|
[Migration] Migrate bitsandbytes support to OOT plugin (#43529)
Signed-off-by: Isotr0py <mozf@mail2.sysu.edu.cn>
Signed-off-by: Isotr0py <Isotr0py@outlook.com>
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2026-08-09 10:27:31 +08:00 |
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Flora Cui
|
7e85d3a42c
|
[ROCm] Enable pinned memory on supported WSL2 kernels (#50126)
Signed-off-by: Flora Cui <flora.cui@amd.com>
|
2026-08-07 10:43:42 -05:00 |
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Sebastian WooandClaude
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4f76c8ad9d
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[Bugfix][Platform] Stop re-initializing NVML on every device-capability check (fixes #50381) (#50393)
Signed-off-by: seewoo <seewoo@ucsc.edu>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-08-07 08:30:00 +00:00 |
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maobaolongandLi, Jiang <jiang1.li@intel.com>
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13726c80fe
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[CPU] Add MLA backend so DeepSeek-V2/V3 can run on CPU (#49453)
Signed-off-by: baoloongmao <baoloongmao@tencent.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-08-06 16:51:41 +08:00 |
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liuzhenweiandKunshang Ji
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8c0f029ac7
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[XPU] update warning of XPU Graph (#50236)
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-08-06 06:33:33 +00:00 |
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Rehan KhanandLi, Jiang <jiang1.li@intel.com>
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0187f4c88e
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[CPU] Enable tcmalloc for s390x (#50841)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-08-05 10:55:39 +08:00 |
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skysnow2001andDouglas Lehr
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f43e1d26e3
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[ROCm] Enable AITER and FP8 inference on GFX120x (#43615)
Signed-off-by: skysnow2001 <skysnow9285@gmail.com>
Co-authored-by: Douglas Lehr <91553416+dllehr-amd@users.noreply.github.com>
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2026-08-03 16:45:37 -05:00 |
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AdrianandClaude
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4fdd3e0b74
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[ROCm][ViT] Detect Triton-AMD kernels at their new aiter location (#40289)
Signed-off-by: Adrian Kurt <info@zzit.ch>
Signed-off-by: Adrian <info@zipfuzapfu.ch>
Co-authored-by: Claude <noreply@anthropic.com>
|
2026-07-31 15:30:09 -04:00 |
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Chaojun ZhangandKunshang Ji
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482cfc20f0
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[XPU] Unify XPU RMSNorm kernels with vllm_c and drop redundant XPU-specific implementation (#46981)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-07-31 17:28:18 +08:00 |
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Xiaochang WuandKunshang Ji
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1d8be5cb44
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[XPU] [BugFix] Add deepseek_v4_fp8 to xpu supported_quantization list (#50434)
Signed-off-by: Wu, Xiaochang <xiaochang.wu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-07-31 11:12:04 +08:00 |
|
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+1
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4f1da84eb5
|
Enable gfx1250 ROCm architecture (#46516)
Signed-off-by: Douglas Lehr <Doug.Lehr@amd.com>
Signed-off-by: jpvillam <juan.villamizar@amd.com>
Signed-off-by: Daniel <danichan@amd.com>
Signed-off-by: Jaden Mathias <jaden.mathias@amd.com>
Signed-off-by: jpvillam <jpvillam@amd.com>
Signed-off-by: Juan Villamizar <100237675+jpvillam-amd@users.noreply.github.com>
Signed-off-by: Douglas Lehr <91553416+dllehr-amd@users.noreply.github.com>
Signed-off-by: Jaden Mathias <Jaden.Mathias@amd.com>
Co-authored-by: Douglas Lehr <Doug.Lehr@amd.com>
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
Co-authored-by: Daniel <danichan@amd.com>
Co-authored-by: Jaden Mathias <jaden.mathias@amd.com>
Co-authored-by: jpvillam <jpvillam@amd.com>
Co-authored-by: root <root@ctheliosr-1b114-f01-2.mnb.dcgpu>
Co-authored-by: Douglas Lehr <91553416+dllehr-amd@users.noreply.github.com>
Co-authored-by: dllehr <douglehr@amd.com>
Co-authored-by: Daniel Chan <Daniel.Chan@amd.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
|
2026-07-31 01:41:12 +00:00 |
|
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+13
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aeeb36b1f1
|
[New model] Kimi K3 (#50000)
Signed-off-by: zjy0516 <riverclouds.zhu@qq.com>
Signed-off-by: Isotr0py <Isotr0py@outlook.com>
Signed-off-by: Bugen Zhao <i@bugenzhao.com>
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
Signed-off-by: Yifan Qiao <yifanqiao@inferact.ai>
Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
Signed-off-by: wzhao18 <wzhao18.sz@gmail.com>
Co-authored-by: Isotr0py <Isotr0py@outlook.com>
Co-authored-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Bugen Zhao <i@bugenzhao.com>
Co-authored-by: Yongye Zhu <zyy1102000@gmail.com>
Co-authored-by: Ziming Huang <zelda.huanghuang@gmail.com>
Co-authored-by: Roger Wang <hey@rogerw.io>
Co-authored-by: Isotr0py <mozf@inferact.ai>
Co-authored-by: aoshen02 <aoshen02@users.noreply.github.com>
Co-authored-by: Woosuk Kwon <woosuk@inferact.ai>
Co-authored-by: Jee Jee Li <jeejeelee@inferact.ai>
Co-authored-by: aoshen02 <aoshen@inferact.ai>
Co-authored-by: Summer Yang <girasoleyang@gmail.com>
Co-authored-by: Kevin H. Luu <khluu000@gmail.com>
Co-authored-by: Bowen Wang <abmfy@icloud.com>
Co-authored-by: gnovack <novackgm@gmail.com>
Co-authored-by: Nick Hill <nickhill123@gmail.com>
Co-authored-by: Yifan Qiao <yifanqiao@inferact.ai>
Co-authored-by: xiaozhoupy <peiyuanzhou1994@gmail.com>
Co-authored-by: Roy Wang <yasong.wang@inferact.ai>
Co-authored-by: Jeff (Junze) Ma <93145857+majunze2001@users.noreply.github.com>
Co-authored-by: Codex <codex@openai.com>
Co-authored-by: Wei Zhao <51183510+wzhao18@users.noreply.github.com>
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2026-07-30 03:49:58 -07:00 |
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yinfengLiu
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f1e8fd27ae
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[ROCm] Add AITER FP8 ViT encoder attention (#49937)
Signed-off-by: Liuyinfeng01 <yinfeliu@amd.com>
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2026-07-30 06:22:10 +00:00 |
|
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Yan Ma
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73af7a362a
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[XPU] Add online fp8 quantization test (#44513)
Signed-off-by: Yan Ma <yan.ma@intel.com>
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2026-07-28 10:34:33 +08:00 |
|
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Chaojun ZhangandKunshang Ji
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bf4f633b4c
|
[XPU] Enable QK Norm + RoPE fusion pass on XPU (#49394)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-07-27 03:22:29 +00:00 |
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liuzhenwei
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318b527cc2
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[XPU] add warning for xpu graph limitations (#49419)
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
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2026-07-25 02:26:15 +00:00 |
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Alejandro Paredes La TorreandShengqi Chen
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0a684ab0c0
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[Bugfix] Fix WSL circular import from pin_memory warning_once (#48444)
Signed-off-by: AlejandroParedesLT <alejandroparedeslatorre@gmail.com>
Co-authored-by: Shengqi Chen <harry-chen@outlook.com>
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2026-07-20 18:30:55 -07:00 |
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Sihan ChenandLi, Jiang <jiang1.li@intel.com>
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4938d44a3b
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[CPU] fixes heterogeneous NIXL KV transfer into CPU_ATTN decode workers (#47871)
Signed-off-by: Spycsh <sihan.chen@intel.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-07-20 07:33:13 +00:00 |
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liuzhenwei
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8502958810
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[XPU] support HND layout (#47975)
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
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2026-07-17 10:54:34 +00:00 |
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liuzhenwei
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d5b1ec2684
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[XPU] allow forcing flash attn for mm_prefix (#48828)
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
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2026-07-17 09:44:18 +00:00 |
|
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Michael GoinandClaude Fable 5
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ecf4aa5ce2
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[Bugfix] Fix FlashInfer non-causal draft attention (DFlash/DSpark) on Blackwell (#48167)
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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2026-07-15 12:44:01 -07:00 |
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Rehan KhanandLi, Jiang <jiang1.li@intel.com>
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9e57de7197
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[CPU] Create Proper Numa topology for s390x (#40714)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-07-13 12:58:43 +08:00 |
|
|
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51878e5b6e
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[2/N][KV-Cache Layout Refactor] Pack K/V into the content dim across attention backends (#44455)
Signed-off-by: Lucas Wilkinson <lwilkins@redhat.com>
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Signed-off-by: Lucas Wilkinson <LucasWilkinson@users.noreply.github.com>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: OpenAI Codex <codex@openai.com>
Co-authored-by: Matthew Bonanni <mbonanni@redhat.com>
Co-authored-by: Nicolò Lucchesi <nlucches@redhat.com>
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2026-07-11 11:11:16 -04:00 |
|
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Li, Jiang
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1171467e91
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[CPU] Fix Qwen-Next SSM type for AMX GDN (#48073)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-07-09 15:09:31 +08:00 |
|
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Tyler Michael Smith
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68b4a1d582
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Fix NVML capability lookup for visible devices (#47892)
Signed-off-by: Tyler Michael Smith <tlrmchlsmth@gmail.com>
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2026-07-08 09:07:44 -04:00 |
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Chaojun Zhang
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440002552e
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[XPU] [Fusion passes] Disable fuse_rope_kvcache_cat_mla & qk_norm_rope_ fusion on XPU (#47962)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
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2026-07-08 09:23:06 +00:00 |
|
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liuzhenwei
|
736f1a5907
|
[XPU] Route mm_prefix models to Triton attention backend (#47688)
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
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2026-07-06 16:52:44 +08:00 |
|
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sychen52andmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
67ff0ae30f
|
Support nvfp4 kv with kv-cache-dtype-skip-layers sliding_window (#42890)
Signed-off-by: Shiyang Chen <shiychen@nvidia.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-07-04 02:29:13 +00:00 |
|
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Chris Leonard
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fbc9ba6d30
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New stable abi cleanup (#46656)
Signed-off-by: Chris Leonard <chleonar@redhat.com>
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2026-07-03 14:02:26 +08:00 |
|
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almayneandLi, Jiang <jiang1.li@intel.com>
|
89e99202f2
|
[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639)
Signed-off-by: Anna Mayne <anna.mayne@arm.com>
Signed-off-by: almayne <anna.mayne@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-30 23:24:40 -07:00 |
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