 wangxiyuan
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73b83949f7
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[Platform] Add check_runner_kv_caches_multi_layer (#51633)
Signed-off-by: wangxiyuan <wangxiyuan1007@gmail.com>
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2026-08-13 19:25:07 +00:00 |
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Chaojun Zhang
|
f863387250
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[XPU] Fix UVA weight offloading (non-pinned-tensor views and static Triton launcher) (#51770)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
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2026-08-11 21:48:44 +08:00 |
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liuzhenweiandKunshang Ji
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8c0f029ac7
|
[XPU] update warning of XPU Graph (#50236)
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-08-06 06:33:33 +00:00 |
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Chaojun ZhangandKunshang Ji
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482cfc20f0
|
[XPU] Unify XPU RMSNorm kernels with vllm_c and drop redundant XPU-specific implementation (#46981)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-07-31 17:28:18 +08:00 |
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Xiaochang WuandKunshang Ji
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1d8be5cb44
|
[XPU] [BugFix] Add deepseek_v4_fp8 to xpu supported_quantization list (#50434)
Signed-off-by: Wu, Xiaochang <xiaochang.wu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-07-31 11:12:04 +08:00 |
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Yan Ma
|
73af7a362a
|
[XPU] Add online fp8 quantization test (#44513)
Signed-off-by: Yan Ma <yan.ma@intel.com>
|
2026-07-28 10:34:33 +08:00 |
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Chaojun ZhangandKunshang Ji
|
bf4f633b4c
|
[XPU] Enable QK Norm + RoPE fusion pass on XPU (#49394)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-07-27 03:22:29 +00:00 |
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liuzhenwei
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318b527cc2
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[XPU] add warning for xpu graph limitations (#49419)
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
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2026-07-25 02:26:15 +00:00 |
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liuzhenwei
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8502958810
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[XPU] support HND layout (#47975)
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
|
2026-07-17 10:54:34 +00:00 |
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liuzhenwei
|
d5b1ec2684
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[XPU] allow forcing flash attn for mm_prefix (#48828)
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
|
2026-07-17 09:44:18 +00:00 |
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Chaojun Zhang
|
440002552e
|
[XPU] [Fusion passes] Disable fuse_rope_kvcache_cat_mla & qk_norm_rope_ fusion on XPU (#47962)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-07-08 09:23:06 +00:00 |
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|
liuzhenwei
|
736f1a5907
|
[XPU] Route mm_prefix models to Triton attention backend (#47688)
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
|
2026-07-06 16:52:44 +08:00 |
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|
Qiming Zhang
|
91055efd36
|
[XPU] C++ implementation for get_memory_info (#47134)
Signed-off-by: mayuyuace <qiming1.zhang@intel.com>
|
2026-06-30 21:34:47 +08:00 |
|
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Chaojun Zhang
|
8cc242335d
|
[XPU] Optimize XPU worker shutdown logic to prevent resource leak (#46433)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-06-30 15:27:21 +08:00 |
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Wentao YeandTJian
|
007b5a52ed
|
[Log] Update to log once (#46511)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: TJian <tunjian.tan@embeddedllm.com>
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2026-06-24 14:45:16 +00:00 |
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Nick Hill
|
7df3d7dada
|
[Core] Ensure memory is pinned prior to async h2d copy (#45424)
Signed-off-by: Nick Hill <nickhill123@gmail.com>
|
2026-06-20 20:02:24 -07:00 |
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Chaojun Zhang
|
2725c84aae
|
[XPU] Enable sequence parallel support for XPU (#38608)
Signed-off-by: chaojun-zhang <chaojun.zhang@intel.com>
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>
|
2026-06-14 19:26:46 -07:00 |
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Yan MaandKunshang Ji
|
02564b4de0
|
[XPU]fallback to TRITON_ATTN for vit attn on xpu when use float32 dtype (#43759)
Signed-off-by: Yan Ma <yan.ma@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-06-03 03:20:21 -07:00 |
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liuzhenweiandKunshang Ji
|
3f3e2702c2
|
[XPU] Enable rms_norm/act quant fusions (#43963)
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-06-02 16:14:41 +00:00 |
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7e33081cee
|
[Attention] Make FlexAttention and FlashAttention use num-blocks first layouts (#42095)
Signed-off-by: Lucas Wilkinson <lwilkins@redhat.com>
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Co-authored-by: Matthew Bonanni <mbonanni@redhat.com>
Co-authored-by: Nicolò Lucchesi <nlucches@redhat.com>
|
2026-05-26 19:55:56 -07:00 |
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|
Xinyu Chen
|
d740e2c029
|
[XPU] update xpu graph usage (#43043)
Signed-off-by: Xinyu Chen <xinyu1.chen@intel.com>
|
2026-05-19 23:09:07 +08:00 |
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|
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f1e3f0e6d6
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[XPU] Use custom op collective behavior (#41354)
Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-05-19 14:14:59 +08:00 |
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Chaojun ZhangandKunshang Ji
|
ccaf5ffaa3
|
[XPU] disable fusion pattern support on XPU platform (#39789)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-04-23 10:07:45 +08:00 |
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|
Hank_
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a4905133f3
|
[xpu][rocm] Update current_platform.supports_fp8() for TritonExperts (#40132)
Signed-off-by: Hank <hcc.mayday@gmail.com>
|
2026-04-22 13:39:40 +02:00 |
|
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Xinyu ChenandKunshang Ji
|
f4ddaf8cf7
|
[XPU] use spawn multiproc method on xpu (#39671)
Signed-off-by: Xinyu Chen <xinyu1.chen@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-04-16 14:42:07 +08:00 |
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f4b42df048
|
[Attention Backend] TurboQuant: 2-bit KV cache compression with 4x capacity (#38479)
Signed-off-by: vibhavagarwal5 <vibhavagarwal5@gmail.com>
Signed-off-by: Michael Goin <mgoin64@gmail.com>
Co-authored-by: Xinyu Chen <xinyu1.chen@intel.com>
Co-authored-by: Michael Goin <mgoin64@gmail.com>
|
2026-04-14 19:57:13 -07:00 |
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Yan Ma
|
ec68d53b2b
|
Add platform manual_seed_all API (#38468)
Signed-off-by: Yan Ma <yan.ma@intel.com>
|
2026-04-10 13:43:50 +08:00 |
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ee3cf45739
|
[XPU] Initial support for GDN attention on Qwen3-next/Qwen3.5 (#33657)
Signed-off-by: Yan Ma <yan.ma@intel.com>
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
Co-authored-by: Chendi Xue <chendi.xue@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-04-03 08:59:11 +08:00 |
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|
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40bb175027
|
[vLLM IR] 1/N Implement IR skeleton and rms_norm op (#33825)
Signed-off-by: Luka Govedič <lgovedic@redhat.com>
Signed-off-by: Xinyu Chen <xinyu1.chen@intel.com>
Signed-off-by: chzhang <chaojun.zhang@intel.com>
Signed-off-by: Luka Govedic <luka.govedic@gmail.com>
Co-authored-by: Xinyu Chen <xinyu1.chen@intel.com>
Co-authored-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Luka Govedič <ProExpertProg@h100-01.nemg-001.lab.rdu2.dc.redhat.com>
|
2026-03-31 22:15:05 -04:00 |
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3b1dbaad4e
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[HMA]Fix corner case when hybrid page_size can not be evenly divided issue (blk_size=64,tp=4) (#37467)
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Signed-off-by: Chendi.Xue <chendi.xue@intel.com>
Co-authored-by: Matthew Bonanni <mbonanni@redhat.com>
Co-authored-by: Nicolò Lucchesi <nlucches@redhat.com>
|
2026-03-30 16:47:30 +00:00 |
|
|
Kunshang Ji
|
6ae8bbd0c2
|
[XPU] Disable xpu graph by default (#38193)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-03-26 01:53:45 -07:00 |
|
|
Kunshang Ji
|
e9ae3f8077
|
[Hardware][XPU] Align memory usage with cuda on xpu (#37029)
Signed-off-by: Kunshang Ji <jikunshang95@gmail.com>
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-03-25 18:14:29 +08:00 |
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|
Kunshang Ji
|
14771f7150
|
[XPU] support MLA model on Intel GPU (#37143)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-03-25 17:43:42 +08:00 |
|
|
Chaojun Zhang
|
82f836d976
|
[XPU] Support LoRA via torch.compile on XPU platform (#36962)
Signed-off-by: chzhang <chaojun.zhang@intel.com>
|
2026-03-13 10:34:59 +00:00 |
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Wuxun Zhang
|
e584dce52b
|
Add XPU MLA Sparse backend for DeepSeek v3.2 (#33230)
Signed-off-by: Zhang, Wuxun <wuxun.zhang@intel.com>
|
2026-03-11 19:19:15 +08:00 |
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Matthew Bonanni
|
77a73458e3
|
Reapply [Attention] Refactor check_and_update_config (#35122)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
|
2026-03-09 07:17:14 -07:00 |
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liuzhenweiandKunshang Ji
|
9dd656f0ea
|
[XPU][NIXL] Add GPUDirect RDMA support for XPU (#35270)
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-03-03 08:42:49 +08:00 |
|
|
Ofir ZafrirandKunshang Ji
|
a07c4c5939
|
[BugFix][XPU] Fix speculative decoding on Intel XPU due to bug with IGC_ForceOCLSIMDWidth=16 (#35298)
Signed-off-by: Ofir Zafrir <ofir.zafrir@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-02-26 07:15:16 +00:00 |
|
|
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35d44b4557
|
[XPU]Support CUDAGraph on XPU Platform (#34482)
Signed-off-by: Xinyu Chen <xinyu1.chen@intel.com>
Co-authored-by: chzhang <chaojun.zhang@intel.com>
Co-authored-by: zhenwei-intel <zhenwei.liu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-02-24 22:22:52 -08:00 |
|
|
Kunshang Ji
|
8ad54a991b
|
[Platform] Add current_platform.num_compute_units interface (#35042)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
Signed-off-by: Kunshang Ji <jikunshang95@gmail.com>
|
2026-02-24 22:22:49 -08:00 |
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|
Yan Ma
|
b1b5e045df
|
[XPU] allow TORCH_SDPA/TRITON_ATTN as XPU vit Backend (#35010)
Signed-off-by: Yan Ma <yan.ma@intel.com>
|
2026-02-23 05:06:44 -08:00 |
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f2c47886fd
|
[Attention] Add FlashInfer Sparse MLA backend (#33451)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Signed-off-by: Lucas Wilkinson <lwilkins@redhat.com>
Co-authored-by: Lucas Wilkinson <lwilkins@redhat.com>
Co-authored-by: Lucas Wilkinson <LucasWilkinson@users.noreply.github.com>
|
2026-02-12 17:21:54 +00:00 |
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|
Kunshang Ji
|
061da6bcf7
|
[XPU] remove common path warning log (#33769)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-02-04 16:40:17 +08:00 |
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Kunshang Ji
|
e10604480b
|
[XPU][1/N] Deprecate ipex and switch to vllm-xpu-kernels for xpu platform (#33379)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-02-02 22:46:10 -08:00 |
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杨朱 · KikiandClaude Opus 4.5
|
1a7894dbdf
|
[Misc] Replace Optional[X] with X | None syntax (#33332)
Signed-off-by: carlory <baofa.fan@daocloud.io>
Co-authored-by: Claude Opus 4.5 <noreply@anthropic.com>
|
2026-01-30 01:56:59 -08:00 |
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|
Matthew Bonanni
|
2612ba9285
|
[1/N][Attention] Restructure attention: move files (#31916)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
|
2026-01-09 13:10:24 -08:00 |
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sihao_li
|
59fe6f298e
|
[XPU]fallback to TRITON_ATTN on xpu when use float32 dtype (#31762)
Signed-off-by: sihao.li <sihao.li@intel.com>
|
2026-01-07 08:10:29 +00:00 |
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sihao_liandKunshang Ji
|
471ddb99a0
|
[XPU] Remove distributed_executor_backend check (#30760)
Signed-off-by: sihao.li <sihao.li@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2025-12-23 21:34:33 -08:00 |
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|
Yan Ma
|
f1c2c20136
|
[XPU] decrease IGC_ForceOCLSIMDWidth for speculative decoding triton-xpu kernel compilation (#30538)
Signed-off-by: Yan Ma <yan.ma@intel.com>
|
2025-12-23 05:22:15 +00:00 |
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Fanli Lin
|
058926d48c
|
[XPU] allow custom workers (e.g. vllm-omni workers) to be used on XPU (#30935)
Signed-off-by: Fanli Lin <fanli.lin@intel.com>
|
2025-12-18 10:16:36 -08:00 |
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