 Kunshang Ji
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fb42e5219e
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[Platform] Replace torch.cuda.mem_get_info with torch.accelerator.get_memory_info (#44825)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
Signed-off-by: Kunshang Ji <jikunshang95@gmail.com>
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2026-06-30 14:39:52 +08:00 |
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bnellnmandRobert Shaw
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bc8481af09
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[MoE Refactor] Standardize Humming MoE experts + utilities (#43373)
Signed-off-by: Bill Nell <bnell@redhat.com>
Co-authored-by: Robert Shaw <114415538+robertgshaw2-redhat@users.noreply.github.com>
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2026-06-29 06:19:29 -07:00 |
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ddd3855a28
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[MoE Backend] add HPC-Ops MoE backend (#45924)
Signed-off-by: chengvjiang <chengvjiang@tencent.com>
Co-authored-by: chengvjiang <chengvjiang@tencent.com>
Co-authored-by: youkaichao <youkaichao@gmail.com>
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2026-06-27 11:18:07 +08:00 |
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Nick Hill
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4e07ca2c92
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[Core] Add VLLM_GPU_SYNC_CHECK env var (#44800)
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2026-06-26 08:24:33 -07:00 |
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guybdandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2396d91e93
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[CPU][Spec Decode] Enable DFlash SD for CPU (#44029)
Signed-off-by: guybd <guy.boudoukh@intel.com>
Signed-off-by: Guy Boudoukh <guy.boudoukh@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-25 15:32:48 +08:00 |
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1aad125815
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[CPU] Enable chunked prefill and prefix caching for qwen3.5 (#46202)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply@anthropic.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-25 03:49:21 +00:00 |
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JartXandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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70749fdcca
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[Feature] Triton INT4 per-token-head KV cache quantization (#40835)
Signed-off-by: JartX <sagformas@epdcenter.es>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-24 10:21:25 +00:00 |
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Roberto L. Castro
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d86c66c981
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[Feat] Add runtime monitor for post-warmup CuTeDSL compilation (#46167)
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2026-06-23 23:33:17 +00:00 |
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hillel.darshanandCursor
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3554ada5d8
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[CPU][Bugfix][Speculative Decoding] Accept USE_FP64_GUMBEL in CPU recovered-tokens sampler (#46069)
Signed-off-by: hillel.darshan <hillel.darshan@intel.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-06-23 11:54:07 +00:00 |
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44d95069e9
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Enable DeepSeek V4 and GLM-5.1 on SM120 (#43477)
Signed-off-by: Zihua Wu <13583761+lucifer1004@users.noreply.github.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: Yongye Zhu <zyy1102000@gmail.com>
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2026-06-22 11:54:14 -07:00 |
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Nick Hill
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7df3d7dada
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[Core] Ensure memory is pinned prior to async h2d copy (#45424)
Signed-off-by: Nick Hill <nickhill123@gmail.com>
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2026-06-20 20:02:24 -07:00 |
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Jee Jee Li
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22cc891108
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[Kernel] Add PDL support for DeepGEMM kernel (#46006)
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
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2026-06-18 20:49:01 +08:00 |
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Micah Williamson
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e945169207
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Revert "[Kernel] Add PDL support for DeepGEMM kernel" (#45999)
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2026-06-17 22:59:48 -07:00 |
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Jee Jee Li
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4403af8fb5
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[Kernel] Add PDL support for DeepGEMM kernel (#42996)
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
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2026-06-17 20:37:17 -07:00 |
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Wentao Ye
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9c7c74bf10
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[Log] Update deepgemm log (#45857)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-06-17 15:34:22 +00:00 |
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Ting SUNandShengqi Chen
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c45f681932
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[Bugfix][Core] Fall back when numactl --membind is blocked in constrained containers (#45438)
Signed-off-by: Ting Sun <suntcrick@gmail.com>
Co-authored-by: Shengqi Chen <harry-chen@outlook.com>
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2026-06-16 09:49:56 -07:00 |
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wang.yuqi
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c4fd9794e9
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[Frontend] Remove AsyncMicrobatchTokenizer. (#45759)
Signed-off-by: wang.yuqi <yuqi.wang@daocloud.io>
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2026-06-16 08:02:11 +00:00 |
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maobaolongandLi, Jiang <jiang1.li@intel.com>
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b675cb7d0f
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[Bugfix][CPU] Honor cgroup memory limit when computing KV cache size (#45086)
Signed-off-by: baoloongmao <baoloongmao@tencent.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-14 19:26:50 -07:00 |
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Ekagra Ranjanandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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e0b9fb1290
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[ASR] Optimize CPU preproc to get 2.5x RTFx via multi-threading (#44612)
Signed-off-by: Ekagra Ranjan <3116519+ekagra-ranjan@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-11 21:05:11 -07:00 |
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wentian-byte
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b8142294b7
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[Bugfix] Restrict FlashInfer cuDNN FP8 ViT attention gate to Blackwell (SM 100) (#45251)
Signed-off-by: Wentian Byte <3400259131@qq.com>
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2026-06-11 16:39:24 +00:00 |
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Michael GoinandClaude
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5edf7ff489
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[Core] Release cached device memory under pressure on UMA GPUs during weight loading (#45179)
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-06-11 17:49:50 +03:00 |
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Michael GoinandClaude
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87c15d46e3
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[Bugfix] Lazily import the humming quantization backend (#44921)
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-06-10 06:06:17 -07:00 |
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jeff.yeandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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7c2aa3108a
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fix: prevent MM cache hang from stale LRU order keys (#43595)
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-08 22:48:31 -07:00 |
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Tyler Michael SmithandClaude Opus 4.6
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e2f993dc41
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[WideEP] Integrate DeepEP v2 (#41183)
Signed-off-by: Tyler Michael Smith <tlrmchlsmth@gmail.com>
Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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2026-06-08 18:07:29 -07:00 |
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bnellnm
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dc68bd8c41
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[MoE Refactor] FusedMoE/MoERunner inversion refactor (#41184)
Signed-off-by: Bill Nell <bnell@redhat.com>
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2026-06-08 10:42:58 -04:00 |
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Yongye Zhu
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b5235fca2e
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[DSv4] Adding TRTLLM gen attention kernel (#43827)
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2026-06-04 07:35:09 -07:00 |
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Wei ZhaoandWei Zhao
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2427094152
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[Feature] Support EPLB for DeepSeek v4 Mega Moe (#43339)
Signed-off-by: wzhao18 <wzhao18.sz@gmail.com>
Co-authored-by: Wei Zhao (Engrg-Hardware 1) <weizha@login-lyris01.lyris.clusters.nvidia.com>
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2026-06-02 10:56:44 -07:00 |
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JooHo Lee
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a045c7425f
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[MM][CG] Profile encoder CUDA graph pool memory (#41714)
Signed-off-by: JooHo Lee <jooho414@gmail.com>
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2026-06-02 12:27:34 +08:00 |
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29d69332aa
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[BugFix] Fix _has_module to verify native deps via trial import (#44035)
Signed-off-by: esmeetu <jasonailu87@gmail.com>
Signed-off-by: Jeffrey Wang <jeffreywang@anyscale.com>
Signed-off-by: Nick Hill <nickhill123@gmail.com>
Co-authored-by: esmeetu <jasonailu87@gmail.com>
Co-authored-by: Nick Hill <nickhill123@gmail.com>
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2026-05-31 22:06:33 -07:00 |
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Vadim GimpelsonandCursor
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bf18d7e0b4
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[Misc][NUMA] Auto-bind to PCT priority cores on DGX B300 + widen EngineCore across shard NUMA nodes (#43270)
Signed-off-by: Vadim Gimpelson <vadim.gimpelson@gmail.com>
Co-authored-by: Cursor <noreply@cursor.com>
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2026-05-29 10:07:44 +08:00 |
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TJian
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0ba46d4b11
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[ROCm][DSV4] Enable Tilelang MHC replacing torch/triton mhc (#43679)
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
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2026-05-28 07:05:28 +00:00 |
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Wentao Yeandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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c02c758ea4
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[Deprecation] Deprecate functions as scheduled for v0.21.0 (#43358)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-05-26 19:56:21 -07:00 |
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Li, Jiang
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65b7a812a2
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[CPU] Experimentally enable Triton and MRV2 (#43225)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-05-22 01:48:17 -07:00 |
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0ddd7dd656
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[Frontend] DP Supervisor (#40841)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Signed-off-by: Robert Shaw <robertgshaw2@gmail.com>
Signed-off-by: Robert Shaw <114415538+robertgshaw2-redhat@users.noreply.github.com>
Co-authored-by: robertgshaw2-redhat <robertgshaw2@gmail.com>
Co-authored-by: Robert Shaw <114415538+robertgshaw2-redhat@users.noreply.github.com>
Co-authored-by: Nick Hill <nickhill123@gmail.com>
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2026-05-21 20:33:16 -07:00 |
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meena-at-workandClaude Sonnet 4.6
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363fc84407
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Integrate flashinfer b12x MoE and FP4 GEMM kernels for SM120/121 (#40082)
Signed-off-by: Meenakshi Venkataraman <meenakshiv@nvidia.com>
Co-authored-by: Claude Sonnet 4.6 <noreply@anthropic.com>
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2026-05-20 17:21:11 +00:00 |
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Wei Zhao
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8c296de63b
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[Perf] Re-enable flashinfer autotune by default and cleanup (#42857)
Signed-off-by: wzhao18 <wzhao18.sz@gmail.com>
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2026-05-18 09:12:27 -07:00 |
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Tianmu Liandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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cac81b6eda
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[CPU Backend] Improve cpu thread utilization (#42666)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-05-18 03:04:41 -07:00 |
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Dipika Sikka
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a7b801e26d
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[MXFP4] Support for linear layers + compressed-tensors integration (#41664)
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2026-05-12 07:49:33 -04:00 |
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Jonathan MamouandBenjamin Chislett
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a54f0d1049
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[CPU] Fix spec decode kernel signatures for synthetic mode compatibility (#41932)
Signed-off-by: jmamou <jonathan.mamou@intel.com>
Signed-off-by: Jonathan Mamou <jonathan.mamou@intel.com>
Co-authored-by: Benjamin Chislett <chislett.ben@gmail.com>
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2026-05-10 12:07:15 +00:00 |
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baonudesifeizhaiandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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bc5fdc1e6a
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Add NVFP4 all-gather GEMM fusion for AsyncTP (#41882)
Signed-off-by: roG0d <baonudesifeizhai@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-05-10 01:13:22 +00:00 |
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Thien Tran
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530d371302
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[DSv4] Improved fused Indexer Q quant kernel (#41428)
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2026-05-09 01:20:32 -07:00 |
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Nick Hill
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989c176c0a
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[Perf][3/n] Eliminate GPU<->CPU syncs in attention impls (#41434)
Signed-off-by: Nick Hill <nickhill123@gmail.com>
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2026-05-07 19:44:24 -07:00 |
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lyd1992
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5d0fd87038
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[CPU][RISC-V] Auto-bind OMP threads and harden nobind path (#40569)
Signed-off-by: liuyudong <liuyudong@iscas.ac.cn>
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2026-05-06 11:38:08 +00:00 |
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Martin Hickey
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6fca518157
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[BugFix][MyPy]: Module has no attribute "sched_getaffinity" [attr-defined] (#41465)
Signed-off-by: Martin Hickey <martin.hickey@ie.ibm.com>
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2026-05-05 13:20:37 +00:00 |
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66dfee7121
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[Bugfix] Fix degenerate KV cache stride causing TMA cudaErrorIllegalInstruction (#40737)
Signed-off-by: David Oy <david@baseten.co>
Signed-off-by: David Oy <58150256+the-david-oy@users.noreply.github.com>
Signed-off-by: David Oy <david.oy@baseten.co>
Co-authored-by: David Oy <david@baseten.co>
Co-authored-by: Claude <claude@anthropic.com>
Co-authored-by: Vadim Gimpelson <156319763+vadiklyutiy@users.noreply.github.com>
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2026-05-03 23:52:18 +00:00 |
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Yongye Zhu
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bcf5cac9fb
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[DSV4] Add knob to enable pre-attn gemm (#41443)
Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
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2026-05-01 12:23:17 -07:00 |
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baonudesifeizhai
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c3868bbbe4
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[compile] Add FlashInfer FP8 async TP fusion and preserve allreduce fusion ordering #27893 (#39505)
Signed-off-by: baonudesifeizhai <baonudesifeizhai@gmail.com>
Signed-off-by: baonudesifeizhai <85092850+baonudesifeizhai@users.noreply.github.com>
Signed-off-by: roG0d <baonudesifeizhai@gmail.com>
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2026-05-01 05:08:34 +00:00 |
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Yongye Zhu
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5aa371dc8e
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[DSV4] Enable Multi-stream for Pre-Attn GEMM (#41061)
Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
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2026-04-28 09:08:55 -07:00 |
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Zhanda ZhuandYubo Gao
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5d5c776444
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[Perf] FP8 FlashInfer Attn for ViT (#38065)
Signed-off-by: Zhanda Zhu <zhandazhu@gmail.com>
Co-authored-by: Yubo Gao <ybgao-nvidia@users.noreply.github.com>
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2026-04-27 13:44:15 +08:00 |
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+7
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4d51588e23
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[Feat] DeepSeek V4 Rebased (#40860)
Signed-off-by: Yifan Qiao <yifanqiao@inferact.ai>
Signed-off-by: Woosuk Kwon <woosuk@inferact.ai>
Signed-off-by: qizixi <zixi@inferact.ai>
Signed-off-by: Jee Jee Li <pandaleefree@gmail.com>
Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
Co-authored-by: Yongye Zhu <zyy1102000@gmail.com>
Co-authored-by: Yongye Zhu <yongye@inferact.ai>
Co-authored-by: Simon Mo <simon@inferact.ai>
Co-authored-by: Bugen Zhao <i@bugenzhao.com>
Co-authored-by: Giancarlo Delfin <gdelfin@inferact.ai>
Co-authored-by: Jee Jee Li <pandaleefree@gmail.com>
Co-authored-by: Nick Hill <nickhill123@gmail.com>
Co-authored-by: Roger Wang <hey@rogerw.io>
Co-authored-by: Roy Wang <yasong.wang@inferact.ai>
Co-authored-by: Woosuk Kwon <woosuk@inferact.ai>
Co-authored-by: youkaichao <youkaichao@gmail.com>
Co-authored-by: Zhewen Li <jerven.vllm@gmail.com>
Co-authored-by: Zijing Liu <liuzijing2014@gmail.com>
Co-authored-by: khluu <khluu000@gmail.com>
Co-authored-by: qizixi <zixi@inferact.ai>
Co-authored-by: Zhewen Li <zhewenli@inferact.ai>
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2026-04-26 18:31:08 -07:00 |
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