 Madeesh KannanandRobert Shaw
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023808c23d
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[Feature] Add support for JetBrains' Mellum v2 code generation model (#43992)
Signed-off-by: Madeesh Kannan <madeeswaran.kannan@jetbrains.com>
Co-authored-by: Robert Shaw <114415538+robertgshaw2-redhat@users.noreply.github.com>
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2026-06-01 10:11:35 -04:00 |
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Wentao Yeandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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985c97a6a8
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[Perf] Optimize cutlass fp8 scaled mm bypassing padding, 20% kernel performance improvement (#43706)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-01 09:05:21 -04:00 |
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zztandJiangyun Zhu
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8796838910
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[Bugfix] fix wrong partial_rotary_factor calculation for bailing_moe model. (#43770)
Signed-off-by: zzt <zengzetang.zzt@antgroup.com>
Co-authored-by: Jiangyun Zhu <riverclouds.zhu@qq.com>
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2026-06-01 02:42:49 -07:00 |
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Uranus
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1f6048abe5
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fix: glm5.1 pp model loading (#42944)
Signed-off-by: UranusSeven <109661872+UranusSeven@users.noreply.github.com>
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2026-06-01 15:14:47 +08:00 |
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nightcitybladeandnightcityblade
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8b8546da1c
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docs: fix MLA attention docstring examples (#44118)
Co-authored-by: nightcityblade <nightcityblade@gmail.com>
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2026-05-31 12:28:38 -07:00 |
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3fd9d2d357
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[CPU][Zen] Route W8A8 and W4A16 linear inference through zentorch on AMD Zen CPUs (#41813)
Signed-off-by: R <Ganesh.R@amd.com>
Signed-off-by: Harshal Adhav <harshal.adhav@amd.com>
Signed-off-by: Aakar Dwivedi <aadwived@amd.com>
Co-authored-by: R <Ganesh.R@amd.com>
Co-authored-by: Harshal Adhav <harshal.adhav@amd.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Michael Goin <mgoin64@gmail.com>
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2026-05-30 14:17:21 -05:00 |
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Wentao Yeandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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e1105064b2
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[Bug] Fix gemma4 MTP IMA issue when TP>1, CUDA error: an illegal memory access was encountered (#43909)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-05-30 10:34:33 -04:00 |
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Jee Jee LiandYiliu Dong
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559d6710bf
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[PERF]MiniMax-M2 gate kernel (#38445)
Signed-off-by: Jee Jee Li <pandaleefree@gmail.com>
Signed-off-by: qianlihuang <91178480+qianlihuang@users.noreply.github.com>
Co-authored-by: Yiliu Dong <91178480+qianlihuang@users.noreply.github.com>
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2026-05-29 18:28:34 -07:00 |
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bnellnm
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187457a952
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Revert "[MoE Refactor] Migrate MoeWNA16Method quantization to MK orac… (#44033)
Signed-off-by: Bill Nell <bnell@redhat.com>
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2026-05-29 16:45:29 -07:00 |
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bnellnm
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7b98f498cd
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[MoE Refactor] Remove supports_expert_map (#43108)
Signed-off-by: Bill Nell <bnell@redhat.com>
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2026-05-29 17:26:56 -04:00 |
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bnellnmandClaude
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106aa92f04
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[MoE Refactor] Migrate MoeWNA16Method quantization to MK oracle (#42647)
Signed-off-by: Bill Nell <bnell@redhat.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-05-29 17:19:31 -04:00 |
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Wentao Ye
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739096a028
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[Bug] Fix torch device issue for MOE permute (#44005)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-05-29 18:55:00 +00:00 |
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bnellnmandClaude
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84b2a8a7e7
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[MoE Refactor] WNA16 MoE backend selection into oracle module (#42553)
Signed-off-by: Bill Nell <bnell@redhat.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-05-29 13:11:17 -04:00 |
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LucainandClaude Opus 4.6
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11dfa3169d
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Add vLLM library info to Hugging Face Hub requests (#43857)
Signed-off-by: Wauplin <lucainp@gmail.com>
Signed-off-by: Lucain Pouget <lucain@huggingface.co>
Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
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2026-05-29 14:04:58 +00:00 |
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frida-anderssonandCursor
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0b56815a24
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[ROCm][Perf] DSv3.2 MI355X TP4 decode-step orchestration cleanup (3 micro-opts) (#42982)
Signed-off-by: Frida Andersson <fanderss@amd.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-05-29 04:26:57 -07:00 |
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MHYangAMDandMHYangAMD
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ab12aab127
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[Bugfix] [ROCm] [DSV4] Fix AITER MXFP4 MoE weight loading and shuffle… (#42595)
Co-authored-by: MHYangAMD <MHYangAMD@users.noreply.github.com>
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2026-05-29 04:08:33 -07:00 |
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JartX
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0cff0741ff
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[Kernel][ROCm] Native W4A16 kernel for AMD RDNA3 (gfx1100) — fp16 + bf16 (#41394)
Signed-off-by: JartX <sagformas@epdcenter.es>
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2026-05-29 11:04:40 +00:00 |
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Joaquín MondéjarandJee Jee Li
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60a7a2214f
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[Bugfix] Fix Step3 pipeline parallel KeyError for residual tensor (#37622)
Co-authored-by: Jee Jee Li <pandaleefree@gmail.com>
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2026-05-29 03:04:02 -07:00 |
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Yintong LuandKunshang Ji
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04516eabc8
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[XPU] add gelu_tanh to xpu moe backend supported activations (#42822)
Signed-off-by: yintong-lu <yintong.lu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-05-29 14:37:20 +08:00 |
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Wentao Yeandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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710f077617
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[Refactor] Remove dead code (#43234)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-05-29 00:29:56 -04:00 |
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Qiming ZhangandKunshang Ji
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9636709372
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[XPU] add scale transpose to prepare_fp8_moe_layer_for_xpu and bump up kernels (#43277)
Signed-off-by: mayuyuace <qiming1.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-05-29 03:22:51 +00:00 |
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Weida Hong
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dfe8ba7c80
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Adjust design around encoder_cudagraph_forward (#42288)
Signed-off-by: Weida Hong <wdhongtw@google.com>
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2026-05-29 03:02:52 +00:00 |
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212deff2ec
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[feat] add GlmgaProcessor specific logits in glm4_1v.py (#43575)
Signed-off-by: JaredforReal <w13431838023@gmail.com>
Signed-off-by: Isotr0py <mozf@mail2.sysu.edu.cn>
Signed-off-by: Isotr0py <Isotr0py@outlook.com>
Co-authored-by: Isotr0py <mozf@mail2.sysu.edu.cn>
Co-authored-by: Isotr0py <Isotr0py@outlook.com>
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2026-05-29 02:56:02 +00:00 |
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Woosuk Kwon
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7bd45da585
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[DSv4] Move mHC tilelang kernels & Don't use CustomOP in dsv4/nvidia (#43905)
Signed-off-by: Woosuk Kwon <woosuk@inferact.ai>
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2026-05-29 10:25:02 +08:00 |
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b690b2bb67
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[Model]Support Step-3.7-Flash (#43859)
Signed-off-by: luotingdan <luotingdan@stepfun.com>
Signed-off-by: Isotr0py <Isotr0py@outlook.com>
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
Co-authored-by: luotingdan <luotingdan@stepfun.com>
Co-authored-by: Isotr0py <Isotr0py@outlook.com>
Co-authored-by: Yu Huang <yuhuang@nvidia.com>
Co-authored-by: Jee Jee Li <jeejeelee@inferact.ai>
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2026-05-28 17:01:48 -07:00 |
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Harry Mellor
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085ac221a3
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Deprecate JAISLMHeadModel (#43784)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-05-28 18:29:12 +00:00 |
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Hua Huang
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9006204e90
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[MM][CG] Avoid over-padding Qwen2.5-VL encoder cudagraph window metadata (#42796)
Signed-off-by: Hua Huang <huah@nvidia.com>
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2026-05-28 11:22:56 -07:00 |
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9aa131f944
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Add Cosmos3 Reasoner model (#43356)
Signed-off-by: Maciej Bala <mbala@nvidia.com>
Signed-off-by: MaciejBalaNV <mbala@nvidia.com>
Co-authored-by: Isotr0py <mozf@mail2.sysu.edu.cn>
Co-authored-by: Isotr0py <2037008807@qq.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: Roger Wang <hey@rogerw.io>
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2026-05-28 09:43:55 -07:00 |
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3207e7680e
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[XPU][MoE] Add WNA16 oracle backend for GPTQ sym-int4 (xpu_fused_moe) (#41426)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-05-28 16:30:48 +00:00 |
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Matthias Gehre
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a9ec46d4b7
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[ROCm][Perf] Support N=5 in wvSplitK skinny GEMM kernels for speculative decoding (#40687)
Signed-off-by: Matthias Gehre <matthias.gehre@amd.com>
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2026-05-28 16:28:21 +00:00 |
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MajidandMajid Taheri Andani
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c08ebebf30
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[Perf] Add do_not_specialize to Mamba SSD chunk kernels (#43803)
Signed-off-by: Majid Taheri Andani <tahemaji@amazon.com>
Co-authored-by: Majid Taheri Andani <tahemaji@amazon.com>
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2026-05-28 15:40:02 +00:00 |
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Li, Jiang
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20d69d100a
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[CPU] Migrate cpu_awq into awq_marlin (#43841)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-05-28 22:36:31 +08:00 |
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zexplorerhjandhaojiangzheng
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f3b2a819f7
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[Perf][KDA] Fuse gate softplus, chunk-local cumsum, and RCP_LN2 scaling (#43667)
Signed-off-by: haojiangzheng <justineric096@gmail.com>
Co-authored-by: haojiangzheng <justineric096@gmail.com>
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2026-05-28 13:47:08 +00:00 |
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Wentao Ye
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64e1218673
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[Perf] Optimize moe permute by pre-allocate buffer, 9~14% kernel performance improvement (#43014)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-05-28 06:18:26 -07:00 |
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a583c84e2b
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[Bugfix][ROCm] Fix Accuracy Drop in Sparse Indexer on gfx950 (#43781)
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
Signed-off-by: vllmellm <vllm.ellm@embeddedllm.com>
Signed-off-by: kliuae <kuanfu.liu@embeddedllm.com>
Co-authored-by: tjtanaa <tunjian.tan@embeddedllm.com>
Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com>
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2026-05-28 03:37:15 -07:00 |
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4ec2817313
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[Model][Bugfix] Rename weight_mapper to hf_to_vllm_mapper in LlamaNemotronVL pooling models (#43581)
Signed-off-by: Jakub Zakrzewski <jzakrzewski@nvidia.com>
Co-authored-by: opencode <noreply@opencode.ai>
Co-authored-by: tomeras91 <57313761+tomeras91@users.noreply.github.com>
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2026-05-28 03:32:22 -07:00 |
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TJian
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0ba46d4b11
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[ROCm][DSV4] Enable Tilelang MHC replacing torch/triton mhc (#43679)
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
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2026-05-28 07:05:28 +00:00 |
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Thien Tran
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e54eff769d
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[Bugfix] Pass routed_scaling_factor to FlashInfer TRTLLM BF16 MoE (#43769)
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2026-05-27 21:29:14 -07:00 |
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Yongye Zhu
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2d2c660104
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[MoE] Remove inplace fused experts mechanism (#43727)
Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
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2026-05-27 20:00:19 -07:00 |
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Benjamin Bartels
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05eec7120e
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Fix RunAI streamer tensor buffer reuse during weight loading (#43464)
Signed-off-by: bbartels <benjamin@bartels.dev>
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2026-05-27 19:16:52 -07:00 |
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amitz-nv
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381edde1b9
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[Bugfix][Kernel] TRTLLM NVFP4 MoE chunking (#43599)
Signed-off-by: amitz-nv <203509407+amitz-nv@users.noreply.github.com>
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2026-05-28 00:36:21 +00:00 |
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Dakai An
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5963c19478
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Fix Qwen3-VL and Qwen3-omni-thinker accuracy degradation from deepstack inputs under torch.compile (#43617)
Signed-off-by: Dakai An <dakaian108@gmail.com>
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2026-05-27 15:34:08 -07:00 |
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Minh VuandWentao Ye
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206b72c982
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[Quantization] Fix Humming RoutedExperts import (#43540)
Signed-off-by: Minh Vu <vuhoangminh97@gmail.com>
Co-authored-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com>
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2026-05-27 10:51:56 -07:00 |
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jatseng-ai
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05c50c721e
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[ROCm] mori: add InterNodeV1LL inter-node kernel selection via VLLM_MORI_INTERNODE_KERNEL (#41751)
Signed-off-by: jatseng-ai <jatseng@amd.com>
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2026-05-28 00:33:32 +08:00 |
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Luciano MartinsandLuciano Martins
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2272062471
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[Kernel] Enable TritonW4A16LinearKernel as CUDA fallback for non-Marlin-aligned W4A16 shapes (#43731)
Signed-off-by: Luciano Martins <lucianommartins@users.noreply.github.com>
Co-authored-by: Luciano Martins <lucianommartins@users.noreply.github.com>
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2026-05-27 18:36:27 +08:00 |
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akii96
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de12f5ca0b
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[ROCm][GPT-OSS] Avoid repeated compile-time cos_sin_cache.to(bf16) casts in rotary path (#42833)
Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
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2026-05-27 16:22:27 +08:00 |
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Nico Holmberg
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7b54690244
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[ROCm][Perf] Expose AITER MoE sorting dispatch policy via env var (#39177)
Signed-off-by: nholmber <nholmber@users.noreply.github.com>
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2026-05-27 13:11:02 +08:00 |
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Xin Yang
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d8eebe6d97
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[Perf] Optimize Fp8BlockScaledMMLinearKernel input_scale tensor using new_empty() (#43677)
Signed-off-by: Xin Yang <xyangx@amazon.com>
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2026-05-26 19:55:52 -07:00 |
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Andreas Karatzas
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5bdb181df5
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[ROCm][CI] Fix ROCm multimodal Qwen2.5-VL activation compile and Phi4MM ragged image mask handling (#43647)
Signed-off-by: Andreas Karatzas <akaratza@amd.com>
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2026-05-26 19:53:34 -07:00 |
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Jee Jee Li
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6e503868ca
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[Kernel] Porting fuse_minimax_qk_norm to manual fusion (#43410)
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
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2026-05-26 13:16:03 -07:00 |
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