 Woosuk KwonandClaude Opus 5.5
|
e1a5086256
|
[Attention] Remove cascade attention (#61126)
Signed-off-by: Woosuk Kwon <woosuk@inferact.ai>
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
|
2026-10-12 10:41:07 -07:00 |
|
|
Praneeth Reddy AandLi, Jiang <jiang1.li@intel.com>
|
1c47ebfc57
|
[Docs] Fix VLLM_CPU_KVCACHE_SPACE default and units (#60053)
Signed-off-by: Praneeth <praneethreddyarikatla@gmail.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-10-09 19:43:55 +08:00 |
|
|
wangxiyuanandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
072d49bb6e
|
[Platform] Support platform-specific MLA prefill backend selection (#56959)
Signed-off-by: wangxiyuan <wangxiyuan1007@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
2026-10-08 15:25:21 +00:00 |
|
|
|
bd42276e1e
|
[Misc][Platform] Check aligned KV block sizes against every attention backend (#58457)
Signed-off-by: Divy <divy@coralbricks.ai>
Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Co-authored-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com>
|
2026-10-04 11:13:20 -04:00 |
|
|
wangxiyuan
|
44257c2e35
|
[Feature] Triton kernel dispatcher (#43048)
Signed-off-by: wangxiyuan <wangxiyuan1007@gmail.com>
|
2026-09-25 04:07:43 +00:00 |
|
|
Li, Jiang
|
b44895cf93
|
[CPU] Use pre-built triton (#58140)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-09-24 16:12:34 +08:00 |
|
|
|
67ddac3ea8
|
[CPU][GDN] Support NIXL DS convolution-state layout (#53300)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: OpenAI Codex <codex@openai.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-09-24 14:55:20 +08:00 |
|
|
DivyandClaude Opus 5
|
e26547adfb
|
[Bugfix] Pick a KV block size supported by every attention backend (#49845)
Signed-off-by: Divy <divy@coralbricks.ai>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
|
2026-09-23 16:36:35 -04:00 |
|
|
|
23cd0346ce
|
[CPU] Align scheduler and NIXL CPU affinity per local rank (#53636)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: OpenAI Codex <noreply@openai.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-09-17 16:43:08 +08:00 |
|
|
Harry MellorandClaude Opus 5
|
8c1557a79c
|
Add pydocstyle to the ruff rules (#52136)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Signed-off-by: Harry Mellor <hej.mellor@gmail.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
|
2026-09-16 16:44:29 +00:00 |
|
|
|
b6ce714354
|
[Bugfix] Format kernel-import errors eagerly so warning_once does not retain them (#54098)
Signed-off-by: Zeyu Wang <zwang86@users.noreply.github.com>
Co-authored-by: Zeyu Wang <zwang86@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
2026-09-15 16:35:54 -04:00 |
|
|
Li, Jiang
|
c3ccc0e957
|
[Model] Add DeepSeek-V4 CPU backend (#55355)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-09-10 14:14:48 +08:00 |
|
|
Tianmu LiandOpenAI Codex
|
c6c33f2b1f
|
[CPU] Support FP16/BF16 persisted GDN state on AMX (#52191)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: OpenAI Codex <noreply@openai.com>
|
2026-08-31 16:32:20 +08:00 |
|
|
Misha GoinandOpenAI Codex
|
f76d71d7ce
|
[CI/Build] Fix CPU platform pre-commit formatting (#52981)
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: OpenAI Codex <codex@openai.com>
|
2026-08-19 10:32:37 -07:00 |
|
|
Dinesh Chitlangia
|
525b7bbb3a
|
[Bugfix][CPU] Enable C++ causal_conv1d GDN path and float32 SSM cache on non-AMX AVX-512BF16 CPUs (#49688)
Signed-off-by: Dinesh Chitlangia <dineshchitlangia@gmail.com>
|
2026-08-19 10:50:59 -05:00 |
|
|
Li, Jiang
|
e4d61d0d22
|
[CPU] Add AMX-only high-performance MLA backend for DeepSeek V2/V3/R1 (#52616)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-08-19 10:28:52 +08:00 |
|
|
Taneem Ibrahim
|
be3f614ff1
|
[CI] Register CPU CI "VLLM_CPU_CI_ENV" environment variable (#52633)
Signed-off-by: Taneem Ibrahim <taneem.ibrahim@gmail.com>
|
2026-08-18 08:28:00 -04:00 |
|
|
wangxiyuan
|
73b83949f7
|
[Platform] Add check_runner_kv_caches_multi_layer (#51633)
Signed-off-by: wangxiyuan <wangxiyuan1007@gmail.com>
|
2026-08-13 19:25:07 +00:00 |
|
|
Kush Zingade
|
78e7fdd1ab
|
[Bugfix][CPU] Make the Apple Silicon BF16 probe fall back instead of raising (#51627)
Signed-off-by: Kush Zingade <kush.zingade@gmail.com>
|
2026-08-11 21:35:07 +08:00 |
|
|
maobaolongandLi, Jiang <jiang1.li@intel.com>
|
13726c80fe
|
[CPU] Add MLA backend so DeepSeek-V2/V3 can run on CPU (#49453)
Signed-off-by: baoloongmao <baoloongmao@tencent.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-08-06 16:51:41 +08:00 |
|
|
Rehan KhanandLi, Jiang <jiang1.li@intel.com>
|
0187f4c88e
|
[CPU] Enable tcmalloc for s390x (#50841)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-08-05 10:55:39 +08:00 |
|
|
Sihan ChenandLi, Jiang <jiang1.li@intel.com>
|
4938d44a3b
|
[CPU] fixes heterogeneous NIXL KV transfer into CPU_ATTN decode workers (#47871)
Signed-off-by: Spycsh <sihan.chen@intel.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-07-20 07:33:13 +00:00 |
|
|
Rehan KhanandLi, Jiang <jiang1.li@intel.com>
|
9e57de7197
|
[CPU] Create Proper Numa topology for s390x (#40714)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-07-13 12:58:43 +08:00 |
|
|
Li, Jiang
|
1171467e91
|
[CPU] Fix Qwen-Next SSM type for AMX GDN (#48073)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-07-09 15:09:31 +08:00 |
|
|
almayneandLi, Jiang <jiang1.li@intel.com>
|
89e99202f2
|
[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639)
Signed-off-by: Anna Mayne <anna.mayne@arm.com>
Signed-off-by: almayne <anna.mayne@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-06-30 23:24:40 -07:00 |
|
|
Kunshang Ji
|
fb42e5219e
|
[Platform] Replace torch.cuda.mem_get_info with torch.accelerator.get_memory_info (#44825)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
Signed-off-by: Kunshang Ji <jikunshang95@gmail.com>
|
2026-06-30 14:39:52 +08:00 |
|
|
|
1aad125815
|
[CPU] Enable chunked prefill and prefix caching for qwen3.5 (#46202)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply@anthropic.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-06-25 03:49:21 +00:00 |
|
|
Wentao YeandTJian
|
007b5a52ed
|
[Log] Update to log once (#46511)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: TJian <tunjian.tan@embeddedllm.com>
|
2026-06-24 14:45:16 +00:00 |
|
|
Rukhaiya2004
|
9f5117820f
|
[HARDWARE][POWER] Enable fp16 support for PowerPC (#46135)
Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com>
|
2026-06-23 13:24:49 +00:00 |
|
|
adhithyamulticoreware
|
bbb6c274c8
|
[Bugfix] Fix gemma4 crash on CPU: guard mem_get_info call (#44615)
Signed-off-by: ADHITHYA BALAKRISHNAN <adhithya.balakrishnan@multicorewareinc.com>
|
2026-06-05 12:47:56 +00:00 |
|
|
Tianmu Liandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
94d3f4d205
|
[CPU Backend] CPU top-k and top-p sampling kernels using Triton (#43633)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
2026-05-29 15:02:39 +08:00 |
|
|
Li, Jiang
|
65b7a812a2
|
[CPU] Experimentally enable Triton and MRV2 (#43225)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-05-22 01:48:17 -07:00 |
|
|
Li, Jiang
|
b4601ad43f
|
[CPU] Add fused GDN support for AMX CPU platform (#42707)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-05-18 03:04:36 -07:00 |
|
|
Fadi ArafehandVadim Gimpelson
|
51f22dcfd0
|
[Feat][CPU] Enable Gated DeltaNet Attention (Qwen 3.5 / 3.6) (#41025)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Vadim Gimpelson <156319763+vadiklyutiy@users.noreply.github.com>
|
2026-05-07 12:57:09 +08:00 |
|
|
|
22524f7a92
|
[Feat] CPU fp8 attn for AMX/AVX-512 (#39445)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-04-29 20:43:21 +08:00 |
|
|
Li, Jiang
|
d02421a7db
|
[CPU] Refactor CPU affinity and memory management (#39781)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-04-17 21:01:08 +08:00 |
|
|
Li, Jiang
|
324a3d2bd8
|
[CI/Build] Improve stability of CPU tests (#39966)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-04-16 21:50:36 +08:00 |
|
|
Fadi Arafehandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
445b7093fd
|
[perf][cpu] Accelerate BF16 GELU with LUT impl on Arm CPUs (#37469)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
2026-04-15 22:26:17 -07:00 |
|
|
Yan Ma
|
ec68d53b2b
|
Add platform manual_seed_all API (#38468)
Signed-off-by: Yan Ma <yan.ma@intel.com>
|
2026-04-10 13:43:50 +08:00 |
|
|
Chendi.Xue
|
ef5a226819
|
[PD][HeteroArch]Fix accuracy issue with CPU_ATTN as Decoder and Flash_ATTN as prefiller (#38935)
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
|
2026-04-09 11:19:07 +08:00 |
|
|
Md. Mekayel Anik
|
d521dcdbcc
|
docs: clarify SMT and OMP acronyms in CpuPlatform (#39085)
|
2026-04-07 17:42:07 -07:00 |
|
|
Ziming Qi
|
2a36d8fb72
|
[Bugfix][CPU] Fix macOS compatibility broken by #36487 (#38970)
Signed-off-by: Ziming (2imi9) <148090931+2imi9@users.noreply.github.com>
|
2026-04-04 14:05:58 +00:00 |
|
|
Anton Ivanov
|
abebd9323d
|
[CPU] Replace OMP initialization (#36487)
Signed-off-by: Anton Ivanov <anton.ivanov@cambridgegreys.com>
|
2026-04-03 18:42:43 +08:00 |
|
|
Matthew Bonanni
|
116f4be405
|
[1/N][Cleanup] Standardize on use of is_quantized_kv_cache (#38659)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
|
2026-04-01 04:08:01 +00:00 |
|
|
Fadi Arafeh
|
34d317dcec
|
[CPU][UX][Perf] Enable tcmalloc by default (#37607)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
|
2026-03-25 20:39:57 +08:00 |
|
|
Li, Jiang
|
3322e26420
|
[Bugfix] Avoid more OpenMP thread reallocation in CPU torch compile (#37538)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-03-19 10:24:39 +00:00 |
|
|
Li, Jiang
|
261801242f
|
[Bugfix] Avoid OpenMP thread reallocation in CPU torch compile (#37391)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-03-18 07:51:39 +00:00 |
|
|
Li, Jiangandgemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
092ace9e3a
|
[UX] Improve UX of CPU backend (#36968)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Li, Jiang <bigpyj64@gmail.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
2026-03-14 09:27:29 +08:00 |
|
|
typer-JandLi, Jiang <jiang1.li@intel.com>
|
4184653775
|
feat: add RISC-V support for CPU backend (v2) (#36578)
Signed-off-by: typer-J <2236066784@qq.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
|
2026-03-10 21:51:39 -07:00 |
|
|
Matthew Bonanni
|
77a73458e3
|
Reapply [Attention] Refactor check_and_update_config (#35122)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
|
2026-03-09 07:17:14 -07:00 |
|