 yzong-rh
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7d2ce5750e
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[Bugfix] Patch Hopper MXFP4 OOB scales reads leading to NaN (#47910)
Signed-off-by: Yifan Zong <yzong@redhat.com>
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2026-07-07 22:51:22 +00:00 |
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vanshbhatia-amdandvanshbhatia-amd
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c8c2f838e7
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Add tuned selective_state_update config for AMD Instinct MI355 (#47767)
Signed-off-by: vanshbhatia-amd <210711135+vanshbhatia-amd@users.noreply.github.com>
Co-authored-by: vanshbhatia-amd <210711135+vanshbhatia-amd@users.noreply.github.com>
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2026-07-07 22:19:08 +00:00 |
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danielafrimi
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0a2965b1b3
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[BugFix] Fix ModelOpt mixed-precision quantization for sparse quantized_layers configs. (#47318)
Signed-off-by: Daniel Afrimi <dafrimi@nvidia.com>
Signed-off-by: <dafrimi@nvidia.com>
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2026-07-07 11:45:13 +00:00 |
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Harry Mellor
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0ed05b6f82
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[CI] Fix Transformers modeling backend LoRA test (#47832)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-07-07 11:40:00 +00:00 |
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c85d72076a
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[HARDWARE][POWER] optimize math functions of VSX power (#47321)
Signed-off-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com>
Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com>
Co-authored-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com>
Co-authored-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
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2026-07-07 09:35:47 +00:00 |
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Netanel Haberandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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066f02ae94
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[MoE] FI autotuning: max bucket = max token count [e.g. DP_size*MNBT] (#47427)
Signed-off-by: Netanel Haber <58652339+netanel-haber@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-07-07 12:08:36 +03:00 |
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Jee Jee Li
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5d23ca47ab
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[Kernel] Applies routed_scaling_factor internally (#47408)
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
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2026-07-07 02:00:54 -07:00 |
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Micah WilliamsonandAndreas Karatzas
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dd5c299fbe
|
[ROCm][Bugfix] Convert ModelOpt FP8 per-channel weights to e4m3fnuz on MI300/MI325 (#47201)
Signed-off-by: Micah Williamson <micah.williamson@amd.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
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2026-07-06 23:24:58 -07:00 |
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Rahul Vishwakarma
|
9dd2465896
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feat(cpu): add CPU support for Mamba ShortConv (#35059)
Signed-off-by: Rahul Vishwakarma <Rahul.Vishwakarma2@ibm.com>
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2026-07-07 10:47:08 +08:00 |
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Jinzhen Linandmgoin
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d891b9bd51
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[Quantization] add humming moe backend to all dense/moe oracles (#41652)
Signed-off-by: Jinzhen Lin <jinzhen.ljz@antgroup.com>
Co-authored-by: mgoin <mgoin64@gmail.com>
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2026-07-06 13:36:07 -07:00 |
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Andrii SkliarandAndrii Skliar
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b1384f5ec6
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Enable B12x backend for non-gated MoEs (like Nemotron) (#43328)
Signed-off-by: Andrii Skliar <askliar@nvidia.com>
Co-authored-by: Andrii Skliar <askliar@nvidia.com>
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2026-07-06 12:40:07 -07:00 |
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Wentao Ye
|
b1c6dba558
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[Refactor] Remove multiple dead code (#47329)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-07-06 07:54:08 -07:00 |
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Kunshang JiandHarry Mellor
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07f9baf756
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Revert "[Platform] Replace torch.cuda.Event with torch.Event (#47140)" (#47668)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
Co-authored-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-07-06 14:18:33 +01:00 |
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Zhenzhong Xuandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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d9c1767cd4
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[INC][ARK] Direct Register Custom Op for ARK (#46361)
Signed-off-by: Zhenzhong1 <zhenzhong.xu@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-07-06 13:45:50 +08:00 |
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Fadi Arafeh
|
f1073c050c
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[CPU][BugFix] Multiple fixes to w4a8_int8 CPU MoE path (#46739)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
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2026-07-06 05:39:20 +00:00 |
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alex101-opsandzc02384840
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f2aaf59151
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[Feature] Support MTP speculative decoding for Bailing hybrid models (#44880)
Signed-off-by: zc02384840 <zc02384840@antgroup.com>
Co-authored-by: zc02384840 <zc02384840@antgroup.com>
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2026-07-06 10:38:50 +08:00 |
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Cheng Jiangandchengvjiang
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95a248faed
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[Attention Backend] HPC_ATTN backend support mtp and dynamic scheduled attention (#47433)
Signed-off-by: chengvjiang <chengvjiang@tencent.com>
Co-authored-by: chengvjiang <chengvjiang@tencent.com>
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2026-07-05 18:18:25 -07:00 |
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Wentao YeandCanlin Guo
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b6cc46ec3b
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[Feature] Support sequence parallel without the need for DP, 1.9%~5.0% E2E Throughput Improvement (#47070)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Signed-off-by: gcanlin <canlinguosdu@gmail.com>
Co-authored-by: Canlin Guo <canlinguosdu@gmail.com>
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2026-07-05 05:41:30 -07:00 |
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Chaojun ZhangandCopilot
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1a308c449c
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[XPU] Add W8A8 FP8 linear kernel with multi-granularity quant support (#43645)
Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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2026-07-04 18:10:01 +08:00 |
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sychen52andmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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67ff0ae30f
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Support nvfp4 kv with kv-cache-dtype-skip-layers sliding_window (#42890)
Signed-off-by: Shiyang Chen <shiychen@nvidia.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-07-04 02:29:13 +00:00 |
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576bf75d0e
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[AMD][EPLB] Enable EPLB for Quark OCP MXFP4 MoE (#47220)
Signed-off-by: okorzh-amd <okorzh-amd@users.noreply.github.com>
Co-authored-by: okorzh-amd <okorzh-amd@users.noreply.github.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
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2026-07-03 14:41:52 -05:00 |
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Andreas Karatzas
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3775d5fcab
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[ROCm][CI] Adding test groups for parity with upstream (#47479)
Signed-off-by: Andreas Karatzas <akaratza@amd.com>
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2026-07-03 19:15:01 +04:00 |
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Luciano MartinsandLuciano Martins
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979f5511d7
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[Bugfix][Gemma4] Keep image bidirectional attention within the sliding window (#47217)
Signed-off-by: Luciano Martins <lucianommartins@users.noreply.github.com>
Co-authored-by: Luciano Martins <lucianommartins@users.noreply.github.com>
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2026-07-02 19:57:41 -07:00 |
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Yuxuan Zhang
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178fd56094
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support GLM-5.2 gate use FP32 (#47410)
Signed-off-by: zRzRzRzRzRzRzR <Yuxuan.Zhang2@liverpool.ac.uk>
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2026-07-02 22:45:39 +08:00 |
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Hiki
|
2665ed704b
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[Bugfix][Kernel] Correct FlashInfer CUTLASS MoE tuning token bound (#46838)
Signed-off-by: Haobin Guo <haobing@nvidia.com>
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2026-07-02 05:11:00 +00:00 |
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Yongye ZhuandClaude Opus 4.8
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fa248139a0
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[MoE] Plumb gemm1_alpha/beta/clamp_limit into TRT-LLM FP8 MoE (#45723)
Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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2026-07-01 14:34:05 -07:00 |
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Yongye Zhu
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d3229431f9
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[DSV4] Better MXFP8 quantization kernel (#47229)
Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
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2026-07-01 14:33:51 -07:00 |
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Harry Mellor
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e7d0fcbc09
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[CI] Fix various failures on main (#47197)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-07-01 10:35:34 +01:00 |
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ed41aa270a
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[ROCm][DSV4] Use aiter mHC pre/post as the default ROCm path (#43950)
Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com>
Signed-off-by: Fangzhou-Ai <fangzhouai@gmail.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-07-01 16:27:42 +08:00 |
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almayneandLi, Jiang <jiang1.li@intel.com>
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89e99202f2
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[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639)
Signed-off-by: Anna Mayne <anna.mayne@arm.com>
Signed-off-by: almayne <anna.mayne@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-30 23:24:40 -07:00 |
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Gabriel Wu
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9a08a5118e
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fix: skip cooperative top-K on SM120 (#47164)
Signed-off-by: Zihua Wu <13583761+lucifer1004@users.noreply.github.com>
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2026-06-30 21:32:54 -07:00 |
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c5200d3565
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[Attention][DSA] support dcp for FLASHINFER_MLA_SPARSE (#46076)
Signed-off-by: zjy0516 <riverclouds.zhu@qq.com>
Signed-off-by: Jingyi Yang <girasoleyang@gmail.com>
Signed-off-by: Lucas Wilkinson <lwilkins@redhat.com>
Signed-off-by: GirasoleY <girasoleyang@gmail.com>
Co-authored-by: Jingyi Yang <girasoleyang@gmail.com>
Co-authored-by: Lucas Wilkinson <lwilkins@redhat.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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2026-07-01 00:32:20 -04:00 |
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Joe RowellandRobert Shaw
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c8d2f3cb14
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[Bugfix] compressed-tensors: allow int8 grouped WNA16 MoE on Marlin (#47154)
Signed-off-by: Joe Rowell <joerowell4@gmail.com>
Co-authored-by: Robert Shaw <114415538+robertgshaw2-redhat@users.noreply.github.com>
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2026-06-30 12:50:46 -07:00 |
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Andreas Karatzas
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c8f9c156a5
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[ROCm][V1][MLA] Clone prefill backend state per metadata builder (#46993)
Signed-off-by: Andreas Karatzas <akaratza@amd.com>
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2026-06-30 11:43:54 -07:00 |
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245888ff77
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[Feature] Detect all2all peer fault with fault tolerance backend and prevent corrupted output (#43637)
Signed-off-by: fangyuchu <fangyuchu@qq.com>
Co-authored-by: Tyler Michael Smith <tlrmchlsmth@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-30 09:00:25 -07:00 |
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Kunshang JiandHarry Mellor
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e840f0d3f5
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[Platform] Replace torch.cuda.Event with torch.Event (#47140)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Co-authored-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-06-30 08:39:59 -07:00 |
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Arsalan Shakil
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00ebf19cca
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[Bugfix][Quant] Raise actionable error instead of bare assert for group-size/TP mismatch (#46230) (#46236)
Signed-off-by: Arsalan Shakil <shakil.arsalan@yahoo.com>
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2026-06-30 14:57:14 +00:00 |
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Harry Mellor
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1ab9522935
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Remove more unnecessary load_weights methods (#47058)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-06-30 15:22:16 +01:00 |
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8cf7c4d8ad
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[Attention Backend] add HPC-Ops Attention backend (#46020)
Signed-off-by: chengvjiang <chengvjiang@tencent.com>
Co-authored-by: chengvjiang <chengvjiang@tencent.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
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2026-06-30 18:17:43 +08:00 |
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Uros Markovic
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81bcced482
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[Bugfix][ROCm] Preserve MoE weight padding for unquantized Triton path (#46381)
Signed-off-by: Uros Markovic <umarkovi@amd.com>
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2026-06-30 14:47:57 +08:00 |
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Summer YangandClaude
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5b4cb69523
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[Bugfix][MLA] Fix LSE log-base mismatch in DCP + FlashInfer MLA decode (#47079)
Signed-off-by: girasoley <girasoleyang@gmail.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-06-29 19:15:02 -07:00 |
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Thien Tran
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43916891b2
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[GDN] Improve kkt kernel of CuteDSL prefill backend (#46346)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
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2026-06-29 18:34:18 -07:00 |
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Andreas KaratzasandTyler Michael Smith
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53f7553f09
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[ROCm][DeepEP] Stabilize high-throughput DBO for DP+EP (#46990)
Signed-off-by: Andreas Karatzas <akaratza@amd.com>
Signed-off-by: Andreas Karatzas <Andreas.Karatzas@amd.com>
Co-authored-by: Tyler Michael Smith <tlrmchlsmth@gmail.com>
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2026-06-29 14:28:02 -07:00 |
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Jason LiandXin Li
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debec6440b
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Add MiniMax-M3 modelopt nvfp4 support (#46756)
Signed-off-by: Xin Li <xinli@nvidia.com>
Signed-off-by: jasonlizhengjian <jasonlizhengjian@gmail.com>
Co-authored-by: Xin Li <xinli@nvidia.com>
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2026-06-29 09:29:39 -07:00 |
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HDCharles
|
379acd4e4f
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[Bugfix][Quantization] Fix W8A8 int-quantized scheme selection regression (#46860)
Signed-off-by: HDCharles <charlesdavidhernandez@gmail.com>
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2026-06-29 15:55:42 +00:00 |
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bnellnmandRobert Shaw
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bc8481af09
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[MoE Refactor] Standardize Humming MoE experts + utilities (#43373)
Signed-off-by: Bill Nell <bnell@redhat.com>
Co-authored-by: Robert Shaw <114415538+robertgshaw2-redhat@users.noreply.github.com>
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2026-06-29 06:19:29 -07:00 |
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Alden LoboandAlden Lobo
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e186107870
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[Bugfix] Use native SiLU activation in CPU fused MoE (#45961)
Signed-off-by: Alden Lobo <alden.lobo@arm.com>
Co-authored-by: Alden Lobo <alden.lobo@arm.com>
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2026-06-29 09:12:20 +00:00 |
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JohnandHarry Mellor
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0e207dac78
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[Bugfix] Transformers backend: apply learned lm_head.bias for tied-embedding models (#46835)
Signed-off-by: John Langford <jl@hunch.net>
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Co-authored-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-06-29 08:59:15 +00:00 |
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Harry Mellor
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5051698e41
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Remove unnecessary load_weights methods (#44589)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-06-29 01:52:23 -07:00 |
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Yuwen Zhou
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58d6a6e60a
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[CPU] Support cpu compressed-tensor w8a8 int8 moe (#42920)
Signed-off-by: yuwenzho <yuwen.zhou@intel.com>
Signed-off-by: Yuwen Zhou <yuwen.zhou@intel.com>
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2026-06-29 03:04:05 +00:00 |
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