 Jiangyun Zhu
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5728da11ea
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Revert #26113 "[Frontend] CompilationConfig overhaul (#20283): deprecate use_inductor in favor of backend, simplify custom_ops" (#26472)
Signed-off-by: zjy0516 <riverclouds.zhu@qq.com>
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2025-10-09 05:43:55 -07:00 |
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Zhiyuan Li
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d24cf322e1
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[Hybrid]: Decouple Kernel Block Size from KV Page Size (#24486)
Signed-off-by: lizhiyuan <uniartisan2017@gmail.com>
Signed-off-by: Zhiyuan Li <uniartisan2017@gmail.com>
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2025-10-08 23:43:39 -07:00 |
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Matt
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de253d63b7
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[Hardware][AMD] Enable FlexAttention backend on ROCm (#26439)
Signed-off-by: Matthew Wong <Matthew.Wong2@amd.com>
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2025-10-09 06:20:18 +00:00 |
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Nicolò Lucchesi
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4ebc9108a7
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[Kernel] Centralize platform kernel import in current_platform.import_kernels (#26286)
Signed-off-by: NickLucche <nlucches@redhat.com>
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2025-10-08 20:25:31 +00:00 |
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76afe4edf8
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[Bugfix] Fix vllm bench ... on CPU-only head nodes (#25283)
Signed-off-by: Aydin Abiar <aydin@anyscale.com>
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Co-authored-by: Aydin Abiar <aydin@anyscale.com>
Co-authored-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Co-authored-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com>
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2025-10-08 16:06:42 +00:00 |
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Harry Mellor
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2f99f2f506
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Tidy vllm/config/__init__.py to only add classes and functions (#26405)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2025-10-08 07:10:00 -07:00 |
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335b28f7d1
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[TPU] Rename tpu_commons to tpu_inference (#26279)
Signed-off-by: Utkarsh Sharma <utksharma@google.com>
Co-authored-by: Utkarsh Sharma <utksharma@google.com>
Co-authored-by: Chengji Yao <chengjiyao@google.com>
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2025-10-07 23:30:52 -07:00 |
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Lucas Wilkinson
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f80e7866c0
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[Misc] Clean up cruft from previous FlashMLA sparse implementation (#26125)
Signed-off-by: Lucas Wilkinson <lwilkins@redhat.com>
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2025-10-08 10:09:34 +08:00 |
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0c824fc46f
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[Frontend] CompilationConfig overhaul (#20283): deprecate use_inductor in favor of backend, simplify custom_ops (#26113)
Signed-off-by: morrison-turnansky <mturnans@redhat.com>
Signed-off-by: Morrison Turnansky <mturnans@redhat.com>
Signed-off-by: Luka Govedič <ProExpertProg@users.noreply.github.com>
Co-authored-by: Luka Govedič <ProExpertProg@users.noreply.github.com>
Co-authored-by: Jiangyun Zhu <riverclouds.zhu@qq.com>
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2025-10-07 12:53:43 -07:00 |
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Gregory Shtrasberg
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f231e5bc21
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[ROCm] Split AITER unified attention into its own backend (#25507)
Signed-off-by: Gregory Shtrasberg <Gregory.Shtrasberg@amd.com>
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2025-10-06 22:49:23 +00:00 |
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Harry Mellor
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d6953beb91
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Convert formatting to use ruff instead of yapf + isort (#26247)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2025-10-05 07:06:22 -07:00 |
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Hank_
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17edd8a807
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[Platform][Kernel] platform-specific kernel loading (#25823)
Signed-off-by: Hank <hcc.mayday@gmail.com>
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2025-10-05 13:25:15 +02:00 |
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ihb2032
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3303cfb4ac
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[Bugfix][Hardware][RISC-V] Limit supported dtypes to float32 to avoid scheduler segfault (#26228)
Signed-off-by: lyd1992 <liuyudong@iscas.ac.cn>
Signed-off-by: ihb2032 <1355790728@qq.com>
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2025-10-05 10:36:54 +00:00 |
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TJian
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9c5ee91b2a
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[ROCm] [VL] [Bugfix] Fix vit flash attn dispatcher logic for ROCm (#26104)
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
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2025-10-02 22:34:53 -07:00 |
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Matthew Bonanni
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2aaa423842
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[Attention] Move Backend enum into registry (#25893)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
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2025-10-02 20:32:24 -07:00 |
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+6
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fa7e254a7f
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[New Model] DeepSeek-V3.2 (Rebased to Main) (#25896)
Signed-off-by: Chen Zhang <zhangch99@outlook.com>
Signed-off-by: youkaichao <youkaichao@gmail.com>
Signed-off-by: Lucas Wilkinson <lwilkins@redhat.com>
Signed-off-by: mgoin <mgoin64@gmail.com>
Signed-off-by: NickLucche <nlucches@redhat.com>
Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
Signed-off-by: Barry Kang <43644113+Barry-Delaney@users.noreply.github.com>
Signed-off-by: Lucia Fang <fanglu@meta.com>
Co-authored-by: Chen Zhang <zhangch99@outlook.com>
Co-authored-by: youkaichao <youkaichao@gmail.com>
Co-authored-by: Lucas Wilkinson <lwilkins@redhat.com>
Co-authored-by: Robert Shaw <114415538+robertgshaw2-redhat@users.noreply.github.com>
Co-authored-by: Lucas Wilkinson <LucasWilkinson@users.noreply.github.com>
Co-authored-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com>
Co-authored-by: mgoin <mgoin64@gmail.com>
Co-authored-by: Lucia Fang <116399278+luccafong@users.noreply.github.com>
Co-authored-by: Lucia Fang <fanglu@meta.com>
Co-authored-by: NickLucche <nlucches@redhat.com>
Co-authored-by: Siyuan Fu <siyuanf@nvidia.com>
Co-authored-by: Matthew Bonanni <mbonanni@redhat.com>
Co-authored-by: Xiaozhu Meng <mxz297@gmail.com>
Co-authored-by: Barry Kang <43644113+Barry-Delaney@users.noreply.github.com>
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2025-09-30 17:14:41 +08:00 |
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Aaron Pham
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6a113d9aed
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[V0 Deprecation] Remove vllm.worker and update according imports (#25901)
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2025-09-29 23:26:11 +00:00 |
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Chenxi YangandChenxi Yang
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d0d138bc55
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[Nixl][P/D] Add cuda2cpu support (HD->DH transfer) (#24690)
Signed-off-by: Chenxi Yang <cxyang@fb.com>
Co-authored-by: Chenxi Yang <cxyang@fb.com>
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2025-09-29 14:31:51 +00:00 |
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Roger Wang
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65ecb4f134
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[Bugfix] Fallback ViT attn backend to SDPA for blackwell (#25851)
Signed-off-by: Roger Wang <hey@rogerw.io>
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2025-09-29 06:03:51 +00:00 |
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Matthew Bonanni
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3468f17ebe
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[V0 deprecation] Remove _VLLM_V1 suffixes from attention backend names (#25489)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Signed-off-by: Matthew Bonanni <mbonanni001@gmail.com>
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2025-09-25 17:37:50 +00:00 |
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chenlangandchenlang
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1e9a77e037
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[Hardware][RISC-V] Add riscv64 support for vLLM with scalar (#22112)
Signed-off-by: chenlang <chen.lang5@zte.com.cn>
Co-authored-by: chenlang <10346245@zte.com.cn>
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2025-09-25 20:46:11 +08:00 |
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Tyler Michael Smith
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fea8006062
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[Logging] Improve log for when DeepEP HT disables CUDA Graphs (#25531)
Signed-off-by: Tyler Michael Smith <tyler@neuralmagic.com>
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2025-09-24 22:43:06 +00:00 |
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Gregory Shtrasberg
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487745ff49
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[ROCm][Bugfix] Only enable +rms_norm based on aiter if not explicitly disabled (#25275)
Signed-off-by: Gregory Shtrasberg <Gregory.Shtrasberg@amd.com>
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2025-09-24 11:24:39 -04:00 |
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Juan Villamizarandjpvillam
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bde2a1a8a4
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[ROCm] Small functional changes for gptoss (#25201)
Signed-off-by: jpvillam <jpvillam@amd.com>
Co-authored-by: jpvillam <jpvillam@amd.com>
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2025-09-23 23:39:50 +00:00 |
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Chendi.Xue
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5774b0a1da
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[NIXL][OOT platform] support nixl_connector with oot platform and other nixl_backend (#25121)
Signed-off-by: Chendi Xue <Chendi.Xue@intel.com>
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2025-09-23 04:17:42 +00:00 |
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Kunshang Ji
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f225ea7dd9
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[XPU] Fix compile_size is None case. (#25433)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
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2025-09-23 03:09:00 +00:00 |
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Isotr0py
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6fa78d8f23
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[V0 deprecation] Remove platform v1 controling interface (#25410)
Signed-off-by: Isotr0py <mozf@mail2.sysu.edu.cn>
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2025-09-23 01:48:12 +00:00 |
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Michael Goin
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239ef0c1ac
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[CI Failure] Fix fp8 kv cache on <SM90 (#25396)
Signed-off-by: mgoin <mgoin64@gmail.com>
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2025-09-22 18:27:51 +00:00 |
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Burkhard Ringlein
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175811e3b5
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[V1][Attention] Split triton_attn in triton-only and rocm specific backends (#24648)
Signed-off-by: Burkhard Ringlein <ngl@zurich.ibm.com>
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2025-09-22 15:20:28 +00:00 |
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Yizhou
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b6f01bd9a7
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refactor: abstract graph mode support into platform interface (#25161)
Signed-off-by: Yizhou Liu <liu_yizhou@outlook.com>
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2025-09-22 10:22:29 +00:00 |
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Woosuk Kwon
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bc6e542d9f
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Remove V0 attention backends (#25351)
Signed-off-by: Woosuk Kwon <woosuk.kwon@berkeley.edu>
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2025-09-21 16:03:28 -07:00 |
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Woosuk Kwon
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0ff8ebb2d7
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[V0 Deprecation] Remove async_output_proc, preemption mode, delay factor (#25334)
Signed-off-by: Woosuk Kwon <woosuk.kwon@berkeley.edu>
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2025-09-21 08:52:32 -07:00 |
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Chendi.Xue
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a6149aa587
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[OOT] Support sync_model_loading for OOT (#25126)
Signed-off-by: Chendi Xue <Chendi.Xue@intel.com>
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2025-09-19 05:41:53 +00:00 |
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Wentao Ye
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d2a30a2d93
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[Bug] Fix torch Compilation Cache Hit Error (#25093)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2025-09-18 12:38:37 -07:00 |
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Li, Jiang
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9fccd04e30
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[Bugfix] Fix Stream usage in CPU model runner and OneDNN kernel check (#25046)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-09-17 05:54:02 -07:00 |
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Woosuk Kwon
|
5801e49776
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[V0 Deprecation] Remove MQLLMEngine (#25019)
Signed-off-by: Woosuk Kwon <woosuk.kwon@berkeley.edu>
Signed-off-by: Woosuk Kwon <woosuk@thinkingmachines.ai>
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2025-09-16 21:29:27 -07:00 |
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Kunshang Ji
|
5206ab20ba
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[XPU] Fix circular import error. (#24927)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
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2025-09-16 03:35:36 +00:00 |
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Nicolò Lucchesi
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2e41f5abca
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[XPU] Set consistent default KV cache layout (#24745)
Signed-off-by: NickLucche <nlucches@redhat.com>
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2025-09-15 18:09:34 +08:00 |
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Victor Ziliang Peng
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973c9d01da
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[Minor] Simplify duplicative device check for cuda (#24793)
Signed-off-by: Ziliang Peng <ziliangdotme@gmail.com>
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2025-09-13 18:28:38 +00:00 |
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Matthew Bonanni
|
7ba32aa60b
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[Attention][FlashInfer] Enable FP8 FlashInfer (TRTLLM) MLA decode (#24705)
Signed-off-by: Matthew Bonanni <mbonanni001@gmail.com>
|
2025-09-12 15:45:53 -06:00 |
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Wenlong Wang
|
72fc8aa412
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[Multi Modal] Add FA3 in VIT (#24347)
Signed-off-by: wwl2755 <wangwenlong2755@gmail.com>
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2025-09-12 21:27:24 +08:00 |
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Matthew Bonanni
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d4fd2768ef
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[Bugfix][Attention] Fix FlashInfer MLA block size logic (#24692)
Signed-off-by: Matthew Bonanni <mbonanni001@gmail.com>
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2025-09-11 22:39:42 +00:00 |
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Mengqing Cao
|
4f6593b058
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[HybridKVCache][Platform] Add support_hybrid_kv_cache for platform (#24646)
Signed-off-by: MengqingCao <cmq0113@163.com>
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2025-09-11 21:47:58 +08:00 |
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Hanjie QiuandMichael Goin
|
dcb28a332b
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[Kernel] Flashinfer MLA (trtllm-gen) decode kernel integration (#21078)
Signed-off-by: hjjq <hanjieq@nvidia.com>
Signed-off-by: Michael Goin <mgoin64@gmail.com>
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: Michael Goin <mgoin64@gmail.com>
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2025-09-10 15:31:10 -07:00 |
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Thien Tran
|
a0933c3bd6
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[Bugfix] Enable FP8 KV cache for FlashInfer and Triton backend on non-sm100 GPUs (#24577)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
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2025-09-10 12:33:41 -07:00 |
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Lifans
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d6069887c6
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[rocm] enable torchao quantization for rocm (#24400)
Signed-off-by: Lifan Shen <lifans@meta.com>
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2025-09-10 06:16:21 -07:00 |
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baonudesifeizhaiandIsotr0py
|
6cbd41909e
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Feature/vit attention unification# 23880 (#23978)
Signed-off-by: Isotr0py <mozf@mail2.sysu.edu.cn>
Co-authored-by: Isotr0py <mozf@mail2.sysu.edu.cn>
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2025-09-10 06:10:14 -07:00 |
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vllmellm
|
7c195d43da
|
[ROCm][Bugfix] Fix Aiter RMSNorm (#23412)
Signed-off-by: vllmellm <vllm.ellm@embeddedllm.com>
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2025-09-10 21:08:03 +08:00 |
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Ignacio Sica
|
3c2156b3af
|
[Hardware][Apple-CPU] Enable native bfloat16 on Apple Silicon (M2 and later) (#24129)
Signed-off-by: ignaciosica <mignacio.sica@gmail.com>
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2025-09-10 03:50:21 +00:00 |
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Wentao Ye
|
a55cf41a09
|
[Compilation][WideEP] Enable Piecewise CUDAGraph for DeepEPHT (#24123)
|
2025-09-09 10:21:10 -04:00 |
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