 Sihan ChenandLi, Jiang <jiang1.li@intel.com>
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4938d44a3b
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[CPU] fixes heterogeneous NIXL KV transfer into CPU_ATTN decode workers (#47871)
Signed-off-by: Spycsh <sihan.chen@intel.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-07-20 07:33:13 +00:00 |
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Rehan KhanandLi, Jiang <jiang1.li@intel.com>
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9e57de7197
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[CPU] Create Proper Numa topology for s390x (#40714)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-07-13 12:58:43 +08:00 |
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Li, Jiang
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1171467e91
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[CPU] Fix Qwen-Next SSM type for AMX GDN (#48073)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-07-09 15:09:31 +08:00 |
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almayneandLi, Jiang <jiang1.li@intel.com>
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89e99202f2
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[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639)
Signed-off-by: Anna Mayne <anna.mayne@arm.com>
Signed-off-by: almayne <anna.mayne@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-30 23:24:40 -07:00 |
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Kunshang Ji
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fb42e5219e
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[Platform] Replace torch.cuda.mem_get_info with torch.accelerator.get_memory_info (#44825)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
Signed-off-by: Kunshang Ji <jikunshang95@gmail.com>
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2026-06-30 14:39:52 +08:00 |
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1aad125815
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[CPU] Enable chunked prefill and prefix caching for qwen3.5 (#46202)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply@anthropic.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-25 03:49:21 +00:00 |
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Wentao YeandTJian
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007b5a52ed
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[Log] Update to log once (#46511)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: TJian <tunjian.tan@embeddedllm.com>
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2026-06-24 14:45:16 +00:00 |
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Rukhaiya2004
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9f5117820f
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[HARDWARE][POWER] Enable fp16 support for PowerPC (#46135)
Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com>
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2026-06-23 13:24:49 +00:00 |
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adhithyamulticoreware
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bbb6c274c8
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[Bugfix] Fix gemma4 crash on CPU: guard mem_get_info call (#44615)
Signed-off-by: ADHITHYA BALAKRISHNAN <adhithya.balakrishnan@multicorewareinc.com>
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2026-06-05 12:47:56 +00:00 |
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Tianmu Liandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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94d3f4d205
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[CPU Backend] CPU top-k and top-p sampling kernels using Triton (#43633)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-05-29 15:02:39 +08:00 |
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Li, Jiang
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65b7a812a2
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[CPU] Experimentally enable Triton and MRV2 (#43225)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-05-22 01:48:17 -07:00 |
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Li, Jiang
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b4601ad43f
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[CPU] Add fused GDN support for AMX CPU platform (#42707)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-05-18 03:04:36 -07:00 |
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Fadi ArafehandVadim Gimpelson
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51f22dcfd0
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[Feat][CPU] Enable Gated DeltaNet Attention (Qwen 3.5 / 3.6) (#41025)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Vadim Gimpelson <156319763+vadiklyutiy@users.noreply.github.com>
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2026-05-07 12:57:09 +08:00 |
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22524f7a92
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[Feat] CPU fp8 attn for AMX/AVX-512 (#39445)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-04-29 20:43:21 +08:00 |
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Li, Jiang
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d02421a7db
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[CPU] Refactor CPU affinity and memory management (#39781)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-04-17 21:01:08 +08:00 |
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Li, Jiang
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324a3d2bd8
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[CI/Build] Improve stability of CPU tests (#39966)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-04-16 21:50:36 +08:00 |
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Fadi Arafehandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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445b7093fd
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[perf][cpu] Accelerate BF16 GELU with LUT impl on Arm CPUs (#37469)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-04-15 22:26:17 -07:00 |
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Yan Ma
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ec68d53b2b
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Add platform manual_seed_all API (#38468)
Signed-off-by: Yan Ma <yan.ma@intel.com>
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2026-04-10 13:43:50 +08:00 |
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Chendi.Xue
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ef5a226819
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[PD][HeteroArch]Fix accuracy issue with CPU_ATTN as Decoder and Flash_ATTN as prefiller (#38935)
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
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2026-04-09 11:19:07 +08:00 |
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Md. Mekayel Anik
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d521dcdbcc
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docs: clarify SMT and OMP acronyms in CpuPlatform (#39085)
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2026-04-07 17:42:07 -07:00 |
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Ziming Qi
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2a36d8fb72
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[Bugfix][CPU] Fix macOS compatibility broken by #36487 (#38970)
Signed-off-by: Ziming (2imi9) <148090931+2imi9@users.noreply.github.com>
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2026-04-04 14:05:58 +00:00 |
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Anton Ivanov
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abebd9323d
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[CPU] Replace OMP initialization (#36487)
Signed-off-by: Anton Ivanov <anton.ivanov@cambridgegreys.com>
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2026-04-03 18:42:43 +08:00 |
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Matthew Bonanni
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116f4be405
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[1/N][Cleanup] Standardize on use of is_quantized_kv_cache (#38659)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
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2026-04-01 04:08:01 +00:00 |
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Fadi Arafeh
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34d317dcec
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[CPU][UX][Perf] Enable tcmalloc by default (#37607)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
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2026-03-25 20:39:57 +08:00 |
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Li, Jiang
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3322e26420
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[Bugfix] Avoid more OpenMP thread reallocation in CPU torch compile (#37538)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-03-19 10:24:39 +00:00 |
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Li, Jiang
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261801242f
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[Bugfix] Avoid OpenMP thread reallocation in CPU torch compile (#37391)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-03-18 07:51:39 +00:00 |
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Li, Jiangandgemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
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092ace9e3a
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[UX] Improve UX of CPU backend (#36968)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Li, Jiang <bigpyj64@gmail.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
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2026-03-14 09:27:29 +08:00 |
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typer-JandLi, Jiang <jiang1.li@intel.com>
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4184653775
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feat: add RISC-V support for CPU backend (v2) (#36578)
Signed-off-by: typer-J <2236066784@qq.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-03-10 21:51:39 -07:00 |
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Matthew Bonanni
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77a73458e3
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Reapply [Attention] Refactor check_and_update_config (#35122)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
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2026-03-09 07:17:14 -07:00 |
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Ma Jianandjiang1.li
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90805ff464
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[CI/Build] CPU release supports both of AVX2 and AVX512 (#35466)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Co-authored-by: jiang1.li <jiang1.li@intel.com>
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2026-02-28 04:35:21 +00:00 |
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f2c47886fd
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[Attention] Add FlashInfer Sparse MLA backend (#33451)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Signed-off-by: Lucas Wilkinson <lwilkins@redhat.com>
Co-authored-by: Lucas Wilkinson <lwilkins@redhat.com>
Co-authored-by: Lucas Wilkinson <LucasWilkinson@users.noreply.github.com>
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2026-02-12 17:21:54 +00:00 |
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Kunshang Ji
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cb9574eb85
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[XPU][9/N] clean up existing ipex code/doc (#34111)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-02-11 00:27:15 -08:00 |
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ZhengHongming888andgemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
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cb62e86f83
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Add NUMA Core binding in nixl_connector for CPU xPyD (#32365)
Signed-off-by: Hongming Zheng <hongming.zheng@intel.com>
Signed-off-by: ZhengHongming888 <hongming.zheng@intel.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
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2026-02-09 15:39:12 +00:00 |
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Matthew Bonanni
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955b43a5a5
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[Bugfix][Attention] Explicitly report support for kv_cache_dtype bfloat16 (#32795)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
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2026-01-22 19:05:18 +00:00 |
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Matthew Bonanni
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2612ba9285
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[1/N][Attention] Restructure attention: move files (#31916)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
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2026-01-09 13:10:24 -08:00 |
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Ning Xie
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c907d22158
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[refactor] refactor memory constants usage (#31865)
Signed-off-by: Andy Xie <andy.xning@gmail.com>
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2026-01-07 18:37:31 +00:00 |
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SameerAsalandSameerAsal
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70e1acefcd
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[BugFix] Fix NUMA node validation in CPU platform (#31520)
Signed-off-by: SameerAsal <SameerAsal@users.noreply.github.com>
Co-authored-by: SameerAsal <SameerAsal@users.noreply.github.com>
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2025-12-31 04:06:49 +00:00 |
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Li, Jiang
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7157596103
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[CPU] Disable async schedule on CPU (#31525)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-12-30 12:34:08 +00:00 |
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Isotr0pyandgemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
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ec154c36ee
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[Platform] Refactor Platform attention backend selection to avoid breakpoint for OOT platform (#30212)
Signed-off-by: Isotr0py <mozf@mail2.sysu.edu.cn>
Signed-off-by: Isotr0py <2037008807@qq.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
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2025-12-15 17:36:07 +00:00 |
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Fadi Arafeh
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f355ad5412
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[CPU][FIX] Fix build failures on Arm CPUs with torch nightly (#30481)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
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2025-12-12 02:09:25 +00:00 |
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Isotr0py
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b952f4d3c3
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[v1] Add PrefixLM support to FlexAttention backend (#27938)
Signed-off-by: Isotr0py <mozf@mail2.sysu.edu.cn>
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2025-12-07 15:51:36 +00:00 |
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gausah01andLi, Jiang <jiang1.li@intel.com>
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28097d5638
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[Bugfix][CPU] Fix CPU KV cache fallback memory allocation (#29604)
Signed-off-by: Gauri Sahnan <gauri.sahnan@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2025-12-04 13:01:15 +08:00 |
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Li, Jiang
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e2f56c309d
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[CPU] Update torch 2.9.1 for CPU backend (#29664)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-11-28 13:37:54 +00:00 |
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Matthew Bonanni
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fc1d8be3dc
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[Attention] Update attention imports (#29540)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
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2025-11-27 11:19:09 -05:00 |
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Cyrus Leung
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638e4196d1
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[Misc] Make SchedulerConfig.max_model_len init-only (#28733)
Signed-off-by: DarkLight1337 <tlleungac@connect.ust.hk>
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2025-11-15 01:59:31 -08:00 |
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Cyrus Leung
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e2741f6cbc
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[Chore] Rename SchedulerConfig.chunked_prefill_enabled (#28735)
Signed-off-by: DarkLight1337 <tlleungac@connect.ust.hk>
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2025-11-14 18:39:57 +00:00 |
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Cyrus Leung
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511a6b611d
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[Config] Clean up SchedulerConfig initialization (#28665)
Signed-off-by: DarkLight1337 <tlleungac@connect.ust.hk>
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2025-11-14 22:41:02 +08:00 |
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Huamin Li
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07a606aa7e
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[CI Failure] Fix backend selection for encoder-only models (#28534)
Signed-off-by: Huamin Li <3ericli@gmail.com>
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2025-11-13 10:11:27 -05:00 |
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wangxiyuan
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10138c92a5
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[V0 deprecation] Deprecate use_v1 parameter (#28112)
Signed-off-by: wangxiyuan <wangxiyuan1007@gmail.com>
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2025-11-12 14:03:52 +00:00 |
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Li, Jiang
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7f829be7d3
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[CPU] Refactor CPU attention backend (#27954)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-11-12 09:43:06 +08:00 |
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