 Huy Do
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7b346ba8ed
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[Bugfix] Propagate compilation_time from workers to main process for TP>1 (#35503)
Signed-off-by: Huy Do <huydhn@gmail.com>
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2026-02-28 05:03:22 +00:00 |
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Ma Jianandjiang1.li
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90805ff464
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[CI/Build] CPU release supports both of AVX2 and AVX512 (#35466)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Co-authored-by: jiang1.li <jiang1.li@intel.com>
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2026-02-28 04:35:21 +00:00 |
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JaewonandLu Fang
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4453ba8d9e
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[Core] Profiler improvements and lazy initialization (#33198)
Signed-off-by: Jaewon Lee <jaewon@meta.com>
Co-authored-by: Lu Fang <30275821+houseroad@users.noreply.github.com>
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2026-02-12 16:16:38 -08:00 |
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Li, Jiang
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05339a7b20
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[Bugfix][CPU] Fix llama4 inference on CPU (#34321)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-02-11 19:07:23 +08:00 |
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ZhengHongming888andgemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
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cb62e86f83
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Add NUMA Core binding in nixl_connector for CPU xPyD (#32365)
Signed-off-by: Hongming Zheng <hongming.zheng@intel.com>
Signed-off-by: ZhengHongming888 <hongming.zheng@intel.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
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2026-02-09 15:39:12 +00:00 |
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Li, Jiang
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07daee132b
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[CI/Build] Parallelize CPU CI tests (#33778)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-02-05 13:53:48 +08:00 |
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smashyalts
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1e86c802d4
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Fix grammar (#33121)
Signed-off-by: smashyalts <smashyalts@gmail.com>
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2026-01-31 09:59:34 -08:00 |
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Fadi Arafeh
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744ef30484
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[CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm (#32792)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
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2026-01-22 18:55:23 +00:00 |
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wangxiyuan
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bb4337b34c
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[Platform] Deprecate seed_everything (#31659)
Signed-off-by: wangxiyuan <wangxiyuan1007@gmail.com>
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2026-01-04 18:34:04 -08:00 |
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e858bfe051
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[Cleanup] Refactor profiling env vars into a CLI config (#29912)
Signed-off-by: Benjamin Chislett <bchislett@nvidia.com>
Signed-off-by: Benjamin Chislett <chislett.ben@gmail.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
Co-authored-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2025-12-09 13:29:33 -05:00 |
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Wentao Ye
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56669c1f29
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[CI] Fix mypy for vllm/v1/worker (#29037)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2025-11-21 11:36:07 +08:00 |
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StanHatkoandLi, Jiang <jiang1.li@intel.com>
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e52e4da971
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[HARDWARE][CPU] Add Option for Disabling Binding to Specific CPU Cores (#27953)
Signed-off-by: Stan Hatko <stan_hatko@live.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2025-11-06 23:47:11 +08:00 |
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Aditya Tewari
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3755c14532
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[CPU] Enable torch profiling (#28130)
Signed-off-by: Aditya Tewari <aditya.tewari@arm.com>
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2025-11-06 07:32:05 +00:00 |
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Harry Mellor
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6c9fdbf725
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[Docs] Replace rst style double-backtick with md single-backtick (#27091)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2025-10-17 02:47:34 -07:00 |
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Harry Mellor
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8fcaaf6a16
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Update Optional[x] -> x | None and Union[x, y] to x | y (#26633)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2025-10-12 09:51:31 -07:00 |
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Harry Mellor
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d6953beb91
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Convert formatting to use ruff instead of yapf + isort (#26247)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2025-10-05 07:06:22 -07:00 |
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Li, Jiang
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eb32335e35
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[CPU] update torch 2.8 and fix missing fields in TorchSDPAMetadata (#25652)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-09-25 13:29:11 +00:00 |
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cascade
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17871983a2
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[Bugfix] Fix sequence parallelism bug when enable pipeline parallelism (#24021)
Signed-off-by: cascade812 <cascade812@outlook.com>
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2025-09-16 04:32:32 +00:00 |
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Li, Jiang
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ad39106b16
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[CPU] Enable data parallel for CPU backend (#23903)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-08-29 02:19:58 -07:00 |
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Nikhil Suryawanshi
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78dba404ad
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[Hardware][IBM Z]Enable v1 for s390x and s390x dockerfile fixes (#22725)
Signed-off-by: Nikhil Suryawanshi <suryawanshin74@gmail.com>
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2025-08-19 04:40:37 +00:00 |
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Ning Xie
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08d5f7113a
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[Misc] refactor function name (#23029)
Signed-off-by: Andy Xie <andy.xning@gmail.com>
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2025-08-17 22:16:21 -07:00 |
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Li, Jiang
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e3a0e43d7f
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[bugfix] Fix auto thread-binding when world_size > 1 in CPU backend and refactor code (#21032)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-07-19 05:13:55 -07:00 |
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Eric Curtin
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ac9fb732a5
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On environments where numa cannot be detected we get 0 (#21115)
Signed-off-by: Eric Curtin <ecurtin@redhat.com>
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2025-07-17 18:52:17 +00:00 |
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6db31e7a27
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[Hardware][PPC64LE] Enable V1 for ppc64le and ARM (#20554)
Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Nikhil Gupta <nikhil.gupta2@arm.com>
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2025-07-08 20:00:41 -07:00 |
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Yang YangandKunshang Ji
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6e2c19ce22
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[Refactor]Abstract Platform Interface for Distributed Backend and Add xccl Support for Intel XPU (#19410)
Signed-off-by: dbyoung18 <yang5.yang@intel.com>
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2025-07-07 04:32:32 +00:00 |
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Jee Jee Li
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1caca5a589
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[Misc] Add SPDX-FileCopyrightText (#20428)
Signed-off-by: Jee Jee Li <pandaleefree@gmail.com>
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2025-07-04 07:40:42 +00:00 |
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Louie TsaiandLi, Jiang <bigpyj64@gmail.com>
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9368cc90b2
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Automatically bind CPU OMP Threads of a rank to CPU ids of a NUMA node. (#17930)
Signed-off-by: Tsai, Louie <louie.tsai@intel.com>
Co-authored-by: Li, Jiang <bigpyj64@gmail.com>
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2025-06-10 06:22:05 +00:00 |
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Li, Jiang
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4555143ea7
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[CPU] V1 support for the CPU backend (#16441)
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2025-06-03 18:43:01 -07:00 |
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