This website requires JavaScript.
Explore
Help
Sign In
iHore
/
vLLM
Watch
8
Star
0
Fork
0
Code
Issues
Pull Requests
Actions
1
Packages
Projects
Releases
Wiki
Activity
Files
00a4e56d8dd470615f0dde2e4c996ed5564da35f
vLLM
/
vllm
/
platforms
T
History
liuzhenwei
and
Kunshang Ji
e599e2c65e
[XPU][P/D] Add XPU support in NixlConnector (
#22436
)
...
Signed-off-by: zhenwei <
zhenwei.liu@intel.com
> Co-authored-by: Kunshang Ji <
kunshang.ji@intel.com
>
2025-09-04 21:03:12 -07:00
..
__init__.py
[TPU] Support Pathways in vLLM (
#21417
)
2025-07-30 10:02:12 -07:00
cpu.py
[CPU] Enable data parallel for CPU backend (
#23903
)
2025-08-29 02:19:58 -07:00
cuda.py
[Attention] FlashAttn MLA (
#14258
)
2025-09-04 02:47:59 -07:00
interface.py
[Attention] FlashAttn MLA (
#14258
)
2025-09-04 02:47:59 -07:00
neuron.py
[Refactor]Abstract Platform Interface for Distributed Backend and Add xccl Support for Intel XPU (
#19410
)
2025-07-07 04:32:32 +00:00
rocm.py
[XPU] Add xpu torch.compile support (
#22609
)
2025-08-27 05:33:27 +00:00
tpu.py
[XPU][P/D] Add XPU support in NixlConnector (
#22436
)
2025-09-04 21:03:12 -07:00
xpu.py
[XPU][P/D] Add XPU support in NixlConnector (
#22436
)
2025-09-04 21:03:12 -07:00