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iHore/vLLM
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Code Issues Pull Requests Actions 2 Packages Projects Releases Wiki Activity
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019e2c3b7ca799e4497a67eb7e49edea361cb90e
vLLM/vllm/v1/sample
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Pleaplusone 77c16df31d [ROCm][Bugfix] Disable hip sampler to fix deepseek's accuracy issue on ROCm (#32413)
Signed-off-by: ganyi <ygan@amd.com>
2026-01-15 16:35:47 +00:00
..
logits_processor
[Perf] Avoid pageable HtoD transfer in MinTokensLogitsProcessor (#29826)
2025-12-02 21:25:52 +00:00
ops
[ROCm][Bugfix] Disable hip sampler to fix deepseek's accuracy issue on ROCm (#32413)
2026-01-15 16:35:47 +00:00
tpu
[Doc]: fixing typos in diverse files (#29492)
2025-11-27 07:15:50 -08:00
__init__.py
[V1] Implement vLLM V1 [1/N] (#9289)
2024-10-22 01:24:07 -07:00
metadata.py
Update Optional[x] -> x | None and Union[x, y] to x | y (#26633)
2025-10-12 09:51:31 -07:00
rejection_sampler.py
[perf][async] support non cpu sync get logprob tensors for spec (#31336)
2026-01-09 21:24:51 +00:00
sampler.py
[BugFix] Fix returned logprobs with spec decode + prefill chunking (#29216)
2025-11-22 22:41:25 +08:00
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