Jiangyun ZhuandTJian 4fe9e6f6e5 [Refactor][GLM-5.3-Flash] Move sparse_attn_indexer_kpool into the model folder and split AMD/NVIDIA (#55358) ...

Signed-off-by: zjy0516 <riverclouds.zhu@qq.com>
Co-authored-by: TJian <tunjian.tan@embeddedllm.com>

2026-09-16 05:50:35 +00:00

..

common

[5/N][warmup][DSv4] Migrate NVIDIA CuTeDSL attention kernels (#53566)

2026-09-12 00:05:59 -04:00

deepseek_v4

[DSA] Wire DeepGEMM sparse MQA logits into the DeepSeek V4.1 indexer (#56254)

2026-09-15 14:07:14 -07:00

deepseek_v32

[Bugfix][DSA] Write nvfp4_ds_mla from the fused norm+rope kernel (#55538)

2026-09-15 00:25:33 +04:00

deepseek_v41

[Perf][DSpark] Add KV-only context insertion across V4.1 cache formats (#56441)

2026-09-15 21:34:55 -07:00

dots3_note

[MRV2] Buffer util simplifications (#56888)

2026-09-15 20:36:51 +00:00

glm5next

[Refactor][GLM-5.3-Flash] Move sparse_attn_indexer_kpool into the model folder and split AMD/NVIDIA (#55358)

2026-09-16 05:50:35 +00:00

hy_v4

[ROCm][CI] Enable HY-V4 model initialization on ROCm (#54405)

2026-09-07 20:55:44 -05:00

inkling

[Refactor] Remove dead kernel code (#56845)

2026-09-15 13:17:53 -07:00

kimi_k3

[Refactor] Remove dead kernel code (#56845)

2026-09-15 13:17:53 -07:00

minimax_m3

[Bugfix][ROCm] Fix MiniMax-M3 fused MXFP8 block scale (#53674)

2026-09-15 21:59:43 -05:00

qwen4_exp

[Qwen3.8-Flash-Next] Fuse PLE residual and QSA output gate (#55309)

2026-09-14 12:16:25 +00:00

__init__.py

[Model Refactoring] Migrate DeepSeek V4 to vllm/models/ [1/N] (#43004)

2026-05-18 19:50:02 -07:00