3 people e5232679a3 [XPU] Add XPU block-scaled W8A8 fp8 path (#39968) ...

Signed-off-by: Wu, Xiaochang <xiaochang.wu@intel.com>
Signed-off-by: Xiaochang Wu <xiaochang.wu@intel.com>
Co-authored-by: Yuxiang <yuxiang.liang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>

2026-06-03 20:16:19 +08:00

..

kernels

[XPU] Add XPU block-scaled W8A8 fp8 path (#39968)

2026-06-03 20:16:19 +08:00

layers

[Bugfix] Update TrtLLM MoE routing methods (#44347)

2026-06-03 02:56:43 -07:00

model_loader

[Bugfix] Convert Gemma4-MM ViT linear layers to vllm native impl (#43798)

2026-06-01 21:41:16 -07:00

models

[Bugfix] Vendor MiniCPMV/MiniCPMO processors to unblock Transformers v5 (#44282)

2026-06-02 07:14:38 -07:00

offloader

[Refactor] Clean up log once scope="local" (#40540)

2026-04-22 16:42:43 -04:00

warmup

[CI failure] Temporarily disable using persistent cache for flashinfer autotune (#43119)

2026-05-19 11:44:32 -07:00

__init__.py

[Platform] Deprecate seed_everything (#31659)

2026-01-04 18:34:04 -08:00

custom_op.py

Add ability to replace oot ops when using lora (#37181)

2026-03-16 18:04:15 -07:00

parameter.py

[Quantization] add humming quantization kernel (#34556)

2026-04-24 09:29:44 -04:00

utils.py

[Bugfix][Rocm]Aiter MoE re-uses existing tensor addresses after weight update. (#40390)

2026-05-06 10:32:26 +00:00