aditi-amd 385d86a6cf [Attention] Add UltraQuant 4-bit KV cache backend (FlyDSL D=256) (#57057) ...

Signed-off-by: Aditi Rana <aditi.rana@amd.com>

2026-10-06 20:42:52 +00:00

..

__init__.py

Add pydocstyle to the ruff rules (#52136)

2026-09-16 16:44:29 +00:00

cpu.py

[Misc][Platform] Check aligned KV block sizes against every attention backend (#58457)

2026-10-04 11:13:20 -04:00

cuda.py

[Core] Model console logging as CLI configuration (#57205)

2026-09-25 11:36:59 +01:00

interface.py

[Attention] Add UltraQuant 4-bit KV cache backend (FlyDSL D=256) (#57057)

2026-10-06 20:42:52 +00:00

rocm.py

[Attention] Add UltraQuant 4-bit KV cache backend (FlyDSL D=256) (#57057)

2026-10-06 20:42:52 +00:00

tpu.py

[Refactor][TPU] Remove torch_xla path and use tpu-inference (#30808)

2026-01-07 16:07:16 +08:00

xpu.py

[Misc][Platform] Check aligned KV block sizes against every attention backend (#58457)

2026-10-04 11:13:20 -04:00

zen_cpu.py

[ZenCPU] AMD Zen CPU Backend with supported dtypes via zentorch weekly (#39967)

2026-04-18 06:22:37 +00:00