Li, Jiang 65b7a812a2 [CPU] Experimentally enable Triton and MRV2 (#43225) ...

Signed-off-by: jiang1.li <jiang1.li@intel.com>

2026-05-22 01:48:17 -07:00

..

__init__.py

Add XPU MLA Sparse backend for DeepSeek v3.2 (#33230)

2026-03-11 19:19:15 +08:00

allocation.py

Add TMA support to fused_moe_lora kernel (#32195)

2026-03-01 10:55:25 +08:00

importing.py

[CPU] Experimentally enable Triton and MRV2 (#43225)

2026-05-22 01:48:17 -07:00

jit_monitor.py

[Feature] Add Triton kernel JIT compilation monitor for inference (#40137)

2026-05-05 14:08:57 +04:00