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1a0b157a2ea46eebd69072f78e5a97ece4f6a2e7
vLLM
/
vllm
/
attention
/
backends
T
History
Li, Jiang
7f829be7d3
[CPU] Refactor CPU attention backend (
#27954
)
...
Signed-off-by: jiang1.li <
jiang1.li@intel.com
>
2025-11-12 09:43:06 +08:00
..
__init__.py
[Core] Refactor Attention Take 2 (
#3462
)
2024-03-25 04:39:33 +00:00
abstract.py
[Attention] Refactor CUDA attention backend selection logic (
#24794
)
2025-11-11 07:40:44 -05:00
registry.py
[CPU] Refactor CPU attention backend (
#27954
)
2025-11-12 09:43:06 +08:00
utils.py
Update
Optional[x]
->
x | None
and
Union[x, y]
to
x | y
(
#26633
)
2025-10-12 09:51:31 -07:00