Liangliang Ma 3da4a1b124 [XPU] add awq format for INCXPULinear (#43404) ...

Signed-off-by: Ma, Liangliang <liangliang.ma@intel.com>

2026-06-22 22:29:13 +08:00

..

kernels

[CPU][RISC-V] Add RVV micro GEMM for WNA16 (#44324)

2026-06-22 12:53:54 +00:00

layers

[XPU] add awq format for INCXPULinear (#43404)

2026-06-22 22:29:13 +08:00

model_loader

[Bugfix][Model] Validate DefaultModelLoader / LoadConfig and fail with clear errors (#45196)

2026-06-17 21:46:33 +00:00

models

[Model] ColQwen3.5: fix retrieval correctness (bias + bidirectional) (#46108)

2026-06-22 17:25:54 +08:00

offloader

[Refactor] Clean up log once scope="local" (#40540)

2026-04-22 16:42:43 -04:00

warmup

[Model] Add MiniMax M3 support (#45381)

2026-06-16 01:01:25 +08:00

__init__.py

[Platform] Deprecate seed_everything (#31659)

2026-01-04 18:34:04 -08:00

custom_op.py

Add ability to replace oot ops when using lora (#37181)

2026-03-16 18:04:15 -07:00

parameter.py

Speed up docs build (#44635)

2026-06-05 14:51:44 +00:00

utils.py

[Bugfix][Rocm]Aiter MoE re-uses existing tensor addresses after weight update. (#40390)

2026-05-06 10:32:26 +00:00