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4147910f1e893ba69aa86a210c73e02ae8a0dfde
vLLM
/
vllm
/
v1
/
core
T
History
Hongxin Xu
and
arlenxu
03da3b52ef
[Bugfix] Refactor to support DP parallel in R3 (
#32306
)
...
Signed-off-by: xhx1022 <
1737006628@qq.com
> Co-authored-by: arlenxu <
arlenxu@tencent.com
>
2026-01-16 15:13:58 +08:00
..
sched
[Bugfix] Refactor to support DP parallel in R3 (
#32306
)
2026-01-16 15:13:58 +08:00
__init__.py
[V1] Implement vLLM V1 [1/N] (
#9289
)
2024-10-22 01:24:07 -07:00
block_pool.py
[Prefix Cache] Include lora_name in BlockStored event for deterministic KV-cache reconstruction (
#27577
)
2025-12-30 00:17:16 +00:00
encoder_cache_manager.py
[Core][MM] Optimize encoder cache manager by operating with embeddings only (
#30475
)
2025-12-16 14:18:17 -08:00
kv_cache_coordinator.py
[Feat][Core] Support multiple KV cache groups in Hybrid KV Coordinator (
#31707
)
2026-01-09 10:53:20 -08:00
kv_cache_manager.py
[Core][Hybrid allocator + connector] Support hybrid allocator + kv cache connector (
#30166
)
2025-12-26 18:25:46 -08:00
kv_cache_metrics.py
[Core][Observability] Add KV cache residency metrics (
#27793
)
2025-12-01 18:27:53 +00:00
kv_cache_utils.py
[BugFix] Assign page_size_padded when unifying kv cache spec. (
#32283
)
2026-01-14 20:10:01 +00:00
single_type_kv_cache_manager.py
[Model] Add support for openPangu moe model (
#28775
)
2025-12-30 08:11:38 -08:00