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429a3da6654facfa792995bbbc75ee64cf83be56
vLLM
/
tests
/
kernels
/
ultraquant
T
History
aditi-amd
385d86a6cf
[Attention] Add UltraQuant 4-bit KV cache backend (FlyDSL D=256) (
#57057
)
...
Signed-off-by: Aditi Rana <
aditi.rana@amd.com
>
2026-10-06 20:42:52 +00:00
..
test_config.py
[Attention] Add UltraQuant 4-bit KV cache backend (FlyDSL D=256) (
#57057
)
2026-10-06 20:42:52 +00:00
test_decode_vs_reference.py
[Attention] Add UltraQuant 4-bit KV cache backend (FlyDSL D=256) (
#57057
)
2026-10-06 20:42:52 +00:00
test_dequant_vs_reference.py
[Attention] Add UltraQuant 4-bit KV cache backend (FlyDSL D=256) (
#57057
)
2026-10-06 20:42:52 +00:00
test_flydsl_decode_d256.py
[Attention] Add UltraQuant 4-bit KV cache backend (FlyDSL D=256) (
#57057
)
2026-10-06 20:42:52 +00:00
test_seam_contract.py
[Attention] Add UltraQuant 4-bit KV cache backend (FlyDSL D=256) (
#57057
)
2026-10-06 20:42:52 +00:00
test_store_vs_reference.py
[Attention] Add UltraQuant 4-bit KV cache backend (FlyDSL D=256) (
#57057
)
2026-10-06 20:42:52 +00:00