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vLLM/docs/features
MOVZXandHinata 43fbd6510b [Qwen4Exp] Serve PLE rows from the loader's mapped checkpoint shards (PR #58815)
Adds an opt-in backend, --engram-config '{"host_file_gather": true}', that
serves Qwen4Exp PLE rows from the checkpoint files through the page cache
instead of allocating the 47.7 GiB table on GPU or in pinned host memory.

- Qwen4ExpPLEFileGatherEmbedding allocates no table rows; load_weights keeps
  the default loader's zero-copy safetensors views of each shard. At bind
  (post-load hook) every view must be file-backed per /proc/self/maps (HF
  cache symlinks work; heap/pinned/anonymous memory is rejected) and the
  shards must cover the whole table.
- Each step, Qwen4ExpModelState.prepare_inputs computes the PLE n-gram ids,
  copies them to pinned host memory, syncs the stream once, issues
  POSIX_FADV_WILLNEED over the coalesced page ranges of the step's rows,
  gathers the rows on the host, and copies them into a fixed device staging
  buffer. The forward reads only the staging buffer, so FULL CUDA graph
  capture is unaffected.
- Rows stay in the checkpoint dtype (FP8 table stays FP8, dequantized on the
  GPU); dummy loads serve zeros; weight reload is rejected; takes precedence
  over cpu_offload; rejected on ROCm and with elastic EP.

Co-Authored-By: Hinata <hinata@idihore.id>
Signed-off-by: MOVZX <movzx@yahoo.com>
2026-09-27 09:54:42 +07:00
..

Features

Compatibility Matrix

The tables below show mutually exclusive features and the support on some hardware.

The symbols used have the following meanings:

  • ✅ = Full compatibility
  • 🟠 = Partial compatibility
  • ❌ = No compatibility
  • ❔ = Unknown or TBD

!!! note Check the ❌ or 🟠 with links to see tracking issue for unsupported feature/hardware combination.

Feature x Feature

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Feature CP APC LoRA SD CUDA graph pooling enc-dec logP prmpt logP async output multi-step mm best-of beam-search prompt-embeds
CP ✅
APC ✅ ✅
LoRA ✅ ✅ ✅
SD ✅ ✅ ❌ ✅
CUDA graph ✅ ✅ ✅ ✅ ✅
pooling 🟠* 🟠* ✅ ❌ ✅ ✅
enc-dec ❌ ❌ ❌ ❌ ✅ ✅ ✅
logP ✅ ✅ ✅ ✅ ✅ ❌ ✅ ✅
prmpt logP ✅ ✅ ✅ ✅ ✅ ❌ ✅ ✅ ✅
async output ✅ ✅ ✅ ❌ ✅ ❌ ❌ ✅ ✅ ✅
multi-step ❌ ✅ ❌ ❌ ✅ ❌ ❌ ✅ ✅ ✅ ✅
mm ✅ ✅ 🟠^ ❔ ✅ ✅ ✅ ✅ ✅ ✅ ❔ ✅
best-of ✅ ✅ ✅ ❌ ✅ ❌ ✅ ✅ ✅ ❔ ❌ ✅ ✅
beam-search ✅ ✅ ✅ ❌ ✅ ❌ ✅ ✅ ✅ ❔ ❌ ❔ ✅ ✅
prompt-embeds ✅ ✅ ✅ ❌ ✅ ❌ ❌ ✅ ❌ ❔ ❔ ✅ ❔ ❔ ✅

* Chunked prefill and prefix caching are only applicable to last-token or all pooling with causal attention.
^ LoRA is only applicable to the language backbone of multimodal models.

Feature x Hardware

Feature Volta Turing Ampere Ada Hopper CPU AMD Intel GPU
CP ❌ ✅ ✅ ✅ ✅ ✅ ✅ ✅
APC ❌ ✅ ✅ ✅ ✅ ✅ ✅ ✅
LoRA ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅
SD ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅
CUDA graph ✅ ✅ ✅ ✅ ✅ ❌ ✅ ❌
pooling ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅
enc-dec ✅ ✅ ✅ ✅ ✅ ✅ ❌ ✅
mm ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅
prompt-embeds ✅ ✅ ✅ ✅ ✅ ✅ ❔ ✅
logP ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅
prmpt logP ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅
async output ✅ ✅ ✅ ✅ ✅ ❌ ❌ ✅
multi-step ✅ ✅ ✅ ✅ ✅ ❌ ✅ ✅
best-of ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅
beam-search ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅

!!! note For information on feature support on Google TPU, please refer to the TPU-Inference Recommended Models and Features documentation.