Yejing LaiandKunshang Ji f651a8a9a4 [XPU][UT]Enable ut qk_norm_rope_fusion (#42486) ...

Signed-off-by: Lai, Yejing <yejing.lai@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>

2026-07-01 07:38:03 +00:00

..

fusion

[Perf] Enable + tune FlashInfer fused allreduce at world_size=16 on SM 10.3 (GB300) (#46392)

2026-06-24 23:04:17 -07:00

ir

Preserve layout-changing clones (#44574)

2026-06-05 20:45:24 -04:00

utility

Speed up docs build (#44635)

2026-06-05 14:51:44 +00:00

__init__.py

[torch.compile] Reorganize vllm/compilation and tests/compile (0/N for vLLM IR) (#33731)

2026-02-06 04:19:49 -08:00

fx_utils.py

[torch.compile] Reorganize vllm/compilation and tests/compile (0/N for vLLM IR) (#33731)

2026-02-06 04:19:49 -08:00

inductor_pass.py

Speed up docs build (#44635)

2026-06-05 14:51:44 +00:00

pass_manager.py

[XPU] Enable sequence parallel support for XPU (#38608)

2026-06-14 19:26:46 -07:00

vllm_inductor_pass.py

[XPU][UT]Enable ut qk_norm_rope_fusion (#42486)

2026-07-01 07:38:03 +00:00