Ekagra RanjanandNicolò Lucchesi cd81cdb399 [Scheduler][ASR] Fix CrossAttn blocks per-request for Variable length encoder inputs (#31058) ...

Signed-off-by: Ekagra Ranjan <3116519+ekagra-ranjan@users.noreply.github.com>
Co-authored-by: Nicolò Lucchesi <nlucches@redhat.com>

2026-02-16 11:08:44 +00:00

..

sched

[Scheduler][ASR] Fix CrossAttn blocks per-request for Variable length encoder inputs (#31058)

2026-02-16 11:08:44 +00:00

__init__.py

[V1] Implement vLLM V1 [1/N] (#9289)

2024-10-22 01:24:07 -07:00

block_pool.py

[V1][Hybrid] Mamba Prefix Caching with align mode (#30877)

2026-01-23 09:56:48 -08:00

encoder_cache_manager.py

[Refactor] Move profiling methods to MM budget (#33559)

2026-02-02 23:27:00 +08:00

kv_cache_coordinator.py

[BugFix] Avoid prefix cache hit in the same schedule step for mamba layers (#29387)

2026-02-10 07:41:16 +00:00

kv_cache_manager.py

[BugFix] Avoid prefix cache hit in the same schedule step for mamba layers (#29387)

2026-02-10 07:41:16 +00:00

kv_cache_metrics.py

[Core][Observability] Add KV cache residency metrics (#27793)

2025-12-01 18:27:53 +00:00

kv_cache_utils.py

[Core][BugFix] Fix PP KV cache sharding memory validation (#33698)

2026-02-10 10:46:24 -05:00

single_type_kv_cache_manager.py

[Hybrid] Enable mamba prefix cache "align" mode with async scheduling (#33997)

2026-02-14 13:15:56 -08:00