3 people f1e3f0e6d6 [XPU] Use custom op collective behavior (#41354) ...

Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>

2026-05-19 14:14:59 +08:00

..

__init__.py

[Platform] Fix RISC-V platform detection (lscpu parsing + non-NUMA meminfo) (#40427)

2026-04-24 04:33:05 +00:00

cpu.py

[CPU] Add fused GDN support for AMX CPU platform (#42707)

2026-05-18 03:04:36 -07:00

cuda.py

[MLA Attention Backend] Add TOKENSPEED_MLA backend for DSR1/Kimi K25 prefill + decode on Blackwell (#41778)

2026-05-13 23:48:02 -07:00

interface.py

platforms: add uses_cpu_device() hook to Platform for DeviceConfig (#42313)

2026-05-12 12:39:17 -07:00

rocm.py

[Quant] Consolidate GPTQ: rename gptq_marlin.py to auto_gptq.py (#38288)

2026-05-15 08:25:52 +08:00

tpu.py

[Refactor][TPU] Remove torch_xla path and use tpu-inference (#30808)

2026-01-07 16:07:16 +08:00

xpu.py

[XPU] Use custom op collective behavior (#41354)

2026-05-19 14:14:59 +08:00

zen_cpu.py

[ZenCPU] AMD Zen CPU Backend with supported dtypes via zentorch weekly (#39967)

2026-04-18 06:22:37 +00:00