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iHore/vLLM
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4adc66f64d56338489d00d94de6e13d95741c4be
vLLM/vllm/v1/sample
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Maximilien de Bayser 5de8d9f111 Remove extra tensor on CPU (#20693)
Signed-off-by: Max de Bayser <mbayser@br.ibm.com>
2025-07-12 14:06:34 +08:00
..
ops
[v1] Re-add fp32 support to v1 engine through FlexAttention (#19754)
2025-07-05 09:41:10 +00:00
tpu
[V1] Decouple GPU and TPU InputBatch (#19778)
2025-06-18 06:38:13 +00:00
__init__.py
[V1] Implement vLLM V1 [1/N] (#9289)
2024-10-22 01:24:07 -07:00
logits_processor.py
Remove extra tensor on CPU (#20693)
2025-07-12 14:06:34 +08:00
metadata.py
[V1] LogitsProcessor programming model (#16728)
2025-07-02 09:10:42 -07:00
rejection_sampler.py
[Misc] Add SPDX-FileCopyrightText (#19100)
2025-06-03 11:20:17 -07:00
sampler.py
[V1] LogitsProcessor programming model (#16728)
2025-07-02 09:10:42 -07:00
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