3 people 4c21d41733 [XPU] Route activation CustomOps to SYCL kernels (#53734) ...

Signed-off-by: Marceli Fylcek <marceli.fylcek@intel.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>

2026-09-01 09:19:52 +08:00

..

determinism

[Perf] Autotune batch invariance triton kernel in blackwell, 33.6% E2E latency reduction (#53649)

2026-08-25 15:06:01 -04:00

hw_agnostic

Hardware-agnostic model definition via HF transformer backend (1/N) (#49458)

2026-08-13 11:21:50 +01:00

kernels

[ROCm] remove VLLM_ROCM_USE_AITER_FP4_ASM_GEMM environment variable; make w4a4 use the preshuffle triton+asm by default (#53141)

2026-08-28 18:59:53 +00:00

layers

[XPU] Route activation CustomOps to SYCL kernels (#53734)

2026-09-01 09:19:52 +08:00

model_loader

[Model] Support Qwen3.8-Flash-Next (#53896)

2026-08-31 05:57:56 +00:00

models

[Bugfix][Spec Decode] Take the DFlash draft's RoPE layout from its own config (#54373)

2026-08-31 18:13:20 -04:00

offloader

[Offloader] Offload submodules that make_layers never reaches (#53120)

2026-08-26 18:37:00 +08:00

warmup

[kernel] Integrate FlashInfer BF16 CuTeDSL Low Latency GEMM (#50572)

2026-08-27 22:29:12 +00:00

__init__.py

[Platform] Deprecate seed_everything (#31659)

2026-01-04 18:34:04 -08:00

custom_op.py

[Bugfix] Reject contradictory custom-op directives (#49134)

2026-07-26 08:42:14 -04:00

parameter.py

Speed up docs build (#44635)

2026-06-05 14:51:44 +00:00

utils.py

[Weight processing] Copy over new_data attributes in replace_parameter (#49601)

2026-08-06 13:03:37 -04:00