Chaojun Zhang 862f2ef893 [XPU] Fix the bug of LoRA logits on the XPU platform (#24081) ...

Signed-off-by: chzhang <chaojun.zhang@intel.com>

2025-09-03 08:21:18 +08:00

..

__init__.py

[TPU] Support Pathways in vLLM (#21417)

2025-07-30 10:02:12 -07:00

cpu.py

[CPU] Enable data parallel for CPU backend (#23903)

2025-08-29 02:19:58 -07:00

cuda.py

[XPU] Add xpu torch.compile support (#22609)

2025-08-27 05:33:27 +00:00

interface.py

[Doc]: fix typos in Python comments (#24001)

2025-08-31 08:21:59 +00:00

neuron.py

[Refactor]Abstract Platform Interface for Distributed Backend and Add xccl Support for Intel XPU (#19410)

2025-07-07 04:32:32 +00:00

rocm.py

[XPU] Add xpu torch.compile support (#22609)

2025-08-27 05:33:27 +00:00

tpu.py

[Kernel] Add FP8 support with FlashMLA backend (#22668)

2025-08-22 02:26:32 +00:00

xpu.py

[XPU] Fix the bug of LoRA logits on the XPU platform (#24081)

2025-09-03 08:21:18 +08:00