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58cde5c026efee42987fbc87681ecbf262f9db2b
vLLM
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vllm
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Andreas Karatzas
3ed7b1e6e0
[ROCm] Validate block_size for explicitly selected attention backends (
#36846
)
...
Signed-off-by: Andreas Karatzas <
akaratza@amd.com
>
2026-03-17 17:04:40 -05:00
..
__init__.py
In-Tree AMD Zen CPU Backend via zentorch [1/N] (
#35970
)
2026-03-15 23:35:35 +00:00
cpu.py
[UX] Improve UX of CPU backend (
#36968
)
2026-03-14 09:27:29 +08:00
cuda.py
[Perf] Set Flashinfer sparse MLA as default backend for FP8 kv cache (
#37252
)
2026-03-17 20:09:20 +00:00
interface.py
In-Tree AMD Zen CPU Backend via zentorch [1/N] (
#35970
)
2026-03-15 23:35:35 +00:00
rocm.py
[ROCm] Validate block_size for explicitly selected attention backends (
#36846
)
2026-03-17 17:04:40 -05:00
tpu.py
[Refactor][TPU] Remove torch_xla path and use tpu-inference (
#30808
)
2026-01-07 16:07:16 +08:00
xpu.py
[XPU] Support LoRA via torch.compile on XPU platform (
#36962
)
2026-03-13 10:34:59 +00:00
zen_cpu.py
In-Tree AMD Zen CPU Backend via zentorch [1/N] (
#35970
)
2026-03-15 23:35:35 +00:00