Logo
Explore Help
Sign In
iHore/vLLM
Watch 8
Star 0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
Files
5bd8c71e792a6d1632fd92fec8c4a1b79b02027e
vLLM/vllm/kernels
T
History
Yanan CaoandClaude Sonnet 4 0b99971352 [Kernel][Helion] Optimize Helion config parsing latency (#40850)
Signed-off-by: Yanan Cao <gmagogsfm@gmail.com>
Co-authored-by: Claude Sonnet 4 <noreply@anthropic.com>
2026-05-07 20:27:34 -07:00
..
helion
[Kernel][Helion] Optimize Helion config parsing latency (#40850)
2026-05-07 20:27:34 -07:00
triton
[Perf] FP8 FlashInfer Attn for ViT (#38065)
2026-04-27 13:44:15 +08:00
__init__.py
[vLLM IR] 1/N Implement IR skeleton and rms_norm op (#33825)
2026-03-31 22:15:05 -04:00
aiter_ops.py
[vLLM IR] 2/N fused_add_rms_norm and maybe_inplace overload (#36823)
2026-05-01 23:41:15 -04:00
oink_ops.py
[vLLM IR] 2/N fused_add_rms_norm and maybe_inplace overload (#36823)
2026-05-01 23:41:15 -04:00
vllm_c.py
[vLLM IR] 2/N fused_add_rms_norm and maybe_inplace overload (#36823)
2026-05-01 23:41:15 -04:00
xpu_ops.py
[vLLM IR] 2/N fused_add_rms_norm and maybe_inplace overload (#36823)
2026-05-01 23:41:15 -04:00
Powered by Gitea Version: 1.27.2 Page: 141ms Template: 7ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API