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vLLM/vllm/distributed/kv_transfer/kv_connector
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Chendi.XueandNicolò Lucchesi c9e665852a [NIXL] heterogeneous block_size support (#26759)
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
Signed-off-by: Chendi.Xue <chendi.xue@intel.com>
Co-authored-by: Nicolò Lucchesi <nicolo.lucchesi@gmail.com>
2025-11-14 21:51:32 -08:00
..
v1
[NIXL] heterogeneous block_size support (#26759)
2025-11-14 21:51:32 -08:00
__init__.py
[Core] Implement disagg prefill by StatelessProcessGroup (#10502)
2024-12-01 19:01:00 -06:00
base.py
[V0 deprecation][P/D] Deprecate v0 KVConnectorBase code (1/2) (#21785)
2025-08-04 19:11:33 -07:00
factory.py
[KV connector][WIP] KV cache proxy based on LMCache multi-process mode (#27902)
2025-11-12 20:25:43 +00:00
utils.py
[Core] Simplify async KV output aggregation (#28327)
2025-11-09 09:44:13 -08:00
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