b2f685834a
Signed-off-by: chengvjiang <chengvjiang@tencent.com> Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai> Signed-off-by: Bugen Zhao <i@bugenzhao.com> Signed-off-by: Jee Jee Li <pandaleefree@gmail.com> Co-authored-by: chengvjiang <chengvjiang@tencent.com> Co-authored-by: Jee Jee Li <jeejeelee@inferact.ai> Co-authored-by: Bugen Zhao <i@bugenzhao.com> Co-authored-by: russellfeng <russellfeng@tencent.com> Co-authored-by: Jee Jee Li <pandaleefree@gmail.com>
37 lines
1.4 KiB
Python
37 lines
1.4 KiB
Python
# SPDX-License-Identifier: Apache-2.0
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# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
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"""HY V4 (``hy_v4``) model — hardware-isolated entry point.
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HY V4 combines three architectural pieces:
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- **iHC** (independent Hyper-Connections): the single residual stream is
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replaced by ``hc_mult`` parallel residual channels, gated per sub-block.
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- **MLA + lightning indexer**: multi-head latent attention with an optional
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DSA-style sparse top-k selection, plus an output gate and a learnable sink.
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- **MoE**: sigmoid-routed experts with a clamped SwiGLU and shared experts.
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The package is organized like `vllm.models.deepseek_v32`: this module is the
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only public entry point and dispatches on the current platform, so registry
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entries never reach into a platform subpackage.
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Only NVIDIA is supported for now. The port also drops the reference
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implementation's HPC/TPCP fusion paths, which depend on infrastructure that
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does not exist in this tree.
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"""
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from vllm.platforms import current_platform
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if current_platform.is_rocm():
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raise NotImplementedError("hy_v4 does not yet support ROCm.")
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elif current_platform.is_xpu():
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raise NotImplementedError("hy_v4 does not yet support XPU.")
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else:
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# Covers Blackwell (sm100) and all other CUDA devices.
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from .nvidia.model import HYV4ForCausalLM
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from .nvidia.mtp import HYV4MTP
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__all__ = [
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"HYV4ForCausalLM",
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"HYV4MTP",
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]
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