3 people 638b1a99cc [CPU][RISC-V] Add RVV path for W4A8 INT4 GEMM (#45269) ...

Signed-off-by: wcy <233313160abc@gmail.com>
Co-authored-by: lyd1992 <liuyudong@iscas.ac.cn>
Co-authored-by: OpenAI Codex <codex@openai.com>

2026-06-25 08:18:10 +00:00

..

mixed_precision

[CPU][RISC-V] Add RVV path for W4A8 INT4 GEMM (#45269)

2026-06-25 08:18:10 +00:00

mxfp4

Fix the E8M0 scale computation in the MXFP4 (W4A4) MOE CUTLASS kernel (#43557)

2026-06-15 06:04:54 -07:00

mxfp8

[Kernel] Add FlashInferCutedslMxfp8LinearKernel (cute-dsl mm_mxfp8) (#46393)

2026-06-23 12:45:49 -07:00

nvfp4

[Kernel][Performance] Add FlashInfer cutedsl NVFP4 GEMM backend (#42235)

2026-06-22 16:17:18 -04:00

scaled_mm

[Bugfix][ROCm] Fix FP8 per-tensor scale rank mismatch causing Inductor assertion failure (#44912)

2026-06-16 20:17:42 -07:00

__init__.py

[Kernel] Add FlashInferCutedslMxfp8LinearKernel (cute-dsl mm_mxfp8) (#46393)

2026-06-23 12:45:49 -07:00

base.py

Add the QuantizedActivation linear-kernel contract (#44260)

2026-06-12 13:48:15 -07:00

zentorch_utils.py

[CPU][Zen] Route W8A8 and W4A16 linear inference through zentorch on AMD Zen CPUs (#41813)

2026-05-30 14:17:21 -05:00