Yejing LaiandKunshang Ji 8dd8b6ed78 [XPU] Fix FP8 block-scaled scheme selection on non-CUDA platforms (#43958) ...

Signed-off-by: Lai, Yejing <yejing.lai@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>

2026-06-18 10:16:20 +08:00

..

kernels

[Bugfix][ROCm] Fix FP8 per-tensor scale rank mismatch causing Inductor assertion failure (#44912)

2026-06-16 20:17:42 -07:00

layers

[XPU] Fix FP8 block-scaled scheme selection on non-CUDA platforms (#43958)

2026-06-18 10:16:20 +08:00

model_loader

[Bugfix][Model] Validate DefaultModelLoader / LoadConfig and fail with clear errors (#45196)

2026-06-17 21:46:33 +00:00

models

[MM][Perf][CG] Support ViT full CUDA graph for Kimi-VL (#41992)

2026-06-17 12:14:01 +00:00

offloader

[Refactor] Clean up log once scope="local" (#40540)

2026-04-22 16:42:43 -04:00

warmup

[Model] Add MiniMax M3 support (#45381)

2026-06-16 01:01:25 +08:00

__init__.py

[Platform] Deprecate seed_everything (#31659)

2026-01-04 18:34:04 -08:00

custom_op.py

Add ability to replace oot ops when using lora (#37181)

2026-03-16 18:04:15 -07:00

parameter.py

Speed up docs build (#44635)

2026-06-05 14:51:44 +00:00

utils.py

[Bugfix][Rocm]Aiter MoE re-uses existing tensor addresses after weight update. (#40390)

2026-05-06 10:32:26 +00:00