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74c5cbcd7b6fa07fa5568ba7f7dfbfedc502964e
vLLM
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vllm
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T
History
Jee Jee Li
e3af5bf3ce
[LoRA] Code cleanup (
#60017
)
...
Signed-off-by: Jee Jee Li <
jeejeelee@inferact.ai
>
2026-10-05 09:15:53 +00:00
..
__init__.py
Add
pydocstyle
to the
ruff
rules (
#52136
)
2026-09-16 16:44:29 +00:00
cpu.py
[Misc][Platform] Check aligned KV block sizes against every attention backend (
#58457
)
2026-10-04 11:13:20 -04:00
cuda.py
[Core] Model console logging as CLI configuration (
#57205
)
2026-09-25 11:36:59 +01:00
interface.py
[LoRA] Code cleanup (
#60017
)
2026-10-05 09:15:53 +00:00
rocm.py
[ROCm][Refactor] Move DeepSeek-V4/V4.1 multi-stream overlap gate to ROCm platform (
#58983
)
2026-09-28 05:46:28 -07:00
tpu.py
[Refactor][TPU] Remove torch_xla path and use tpu-inference (
#30808
)
2026-01-07 16:07:16 +08:00
xpu.py
[Misc][Platform] Check aligned KV block sizes against every attention backend (
#58457
)
2026-10-04 11:13:20 -04:00
zen_cpu.py
[ZenCPU] AMD Zen CPU Backend with supported dtypes via zentorch weekly (
#39967
)
2026-04-18 06:22:37 +00:00