Zhang Xiangze 7bdb42b2f2 [CPU]Avoid repeated random sample compile (#28260) ...

Signed-off-by: Zhang Xiangze <Xiangze.Zhang@arm.com>

2025-11-07 11:03:57 +00:00

..

logits_processor

[Bugfix] Validate custom logits processor xargs for online serving (#27560)

2025-11-05 16:53:33 +00:00

ops

[CPU]Avoid repeated random sample compile (#28260)

2025-11-07 11:03:57 +00:00

tpu

[V1][Spec Decode] Fix greedy temperature detection after sampler refactor (#27077)

2025-10-17 13:27:47 -07:00

__init__.py

[V1] Implement vLLM V1 [1/N] (#9289)

2024-10-22 01:24:07 -07:00

metadata.py

Update Optional[x] -> x | None and Union[x, y] to x | y (#26633)

2025-10-12 09:51:31 -07:00

rejection_sampler.py

[V1][spec decode] return logprobs for spec decoding (#26060)

2025-10-22 22:59:59 -07:00

sampler.py

[Chore] Separate out vllm.utils.platform_utils.py (#27374)

2025-10-23 19:08:06 +00:00