Sihan ChenandLi, Jiang <jiang1.li@intel.com> 4938d44a3b [CPU] fixes heterogeneous NIXL KV transfer into CPU_ATTN decode workers (#47871) ...

Signed-off-by: Spycsh <sihan.chen@intel.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>

2026-07-20 07:33:13 +00:00

..

__init__.py

[Core] Ensure memory is pinned prior to async h2d copy (#45424)

2026-06-20 20:02:24 -07:00

cpu.py

[CPU] fixes heterogeneous NIXL KV transfer into CPU_ATTN decode workers (#47871)

2026-07-20 07:33:13 +00:00

cuda.py

[Bugfix] Fix FlashInfer non-causal draft attention (DFlash/DSpark) on Blackwell (#48167)

2026-07-15 12:44:01 -07:00

interface.py

Fix NVML capability lookup for visible devices (#47892)

2026-07-08 09:07:44 -04:00

rocm.py

[2/N][KV-Cache Layout Refactor] Pack K/V into the content dim across attention backends (#44455)

2026-07-11 11:11:16 -04:00

tpu.py

[Refactor][TPU] Remove torch_xla path and use tpu-inference (#30808)

2026-01-07 16:07:16 +08:00

xpu.py

[XPU] support HND layout (#47975)

2026-07-17 10:54:34 +00:00

zen_cpu.py

[ZenCPU] AMD Zen CPU Backend with supported dtypes via zentorch weekly (#39967)

2026-04-18 06:22:37 +00:00