Gregory Shtrasberg 56c976c1b5 [ROCm] Enable fused_silu_mul_block_quant on ROCm (#38817) ...

Signed-off-by: Gregory Shtrasberg <Gregory.Shtrasberg@amd.com>

2026-04-08 11:23:32 -05:00

..

fusion

[ROCm] Enable fused_silu_mul_block_quant on ROCm (#38817)

2026-04-08 11:23:32 -05:00

ir

Fix multiline-format string for python 3.10 (#38739)

2026-04-02 03:19:35 +00:00

utility

[ROCm]: fix aiter rope functionalization (#35533)

2026-02-27 22:42:30 +00:00

__init__.py

[torch.compile] Reorganize vllm/compilation and tests/compile (0/N for vLLM IR) (#33731)

2026-02-06 04:19:49 -08:00

fx_utils.py

[torch.compile] Reorganize vllm/compilation and tests/compile (0/N for vLLM IR) (#33731)

2026-02-06 04:19:49 -08:00

inductor_pass.py

[torch.compile] Reorganize vllm/compilation and tests/compile (0/N for vLLM IR) (#33731)

2026-02-06 04:19:49 -08:00

pass_manager.py

[mla] Support fused FP8/NVFP4 output quantization in MLA attention (#35792) (#36205)

2026-04-02 21:16:11 -04:00

vllm_inductor_pass.py

[vLLM IR] 1/N Implement IR skeleton and rms_norm op (#33825)

2026-03-31 22:15:05 -04:00