3 people 9c3fe9936b Flashinfer cuDNN backend for Qwen3 VL ViT attention (#34580) ...

Signed-off-by: Max Hu <maxhu@nvidia.com>
Signed-off-by: Max Hu <hyoung2991@gmail.com>
Co-authored-by: Max Hu <maxhu@nvidia.com>
Co-authored-by: Shang Wang <shangw@nvidia.com>

2026-02-27 20:20:23 +08:00

..

__init__.py

[XPU] remove common path warning log (#33769)

2026-02-04 16:40:17 +08:00

cpu.py

[Attention] Add FlashInfer Sparse MLA backend (#33451)

2026-02-12 17:21:54 +00:00

cuda.py

Flashinfer cuDNN backend for Qwen3 VL ViT attention (#34580)

2026-02-27 20:20:23 +08:00

interface.py

[ROCm] Add extra step in config initialization to populate custom ops before compilation config init (#34848)

2026-02-26 16:05:40 +08:00

rocm.py

[ROCm] Add extra step in config initialization to populate custom ops before compilation config init (#34848)

2026-02-26 16:05:40 +08:00

tpu.py

[Refactor][TPU] Remove torch_xla path and use tpu-inference (#30808)

2026-01-07 16:07:16 +08:00

xpu.py

[BugFix][XPU] Fix speculative decoding on Intel XPU due to bug with IGC_ForceOCLSIMDWidth=16 (#35298)

2026-02-26 07:15:16 +00:00