4 people 827a2af806 [Kernel] Gemma-4 FA4 FP8 Kernel (#48666) ...

Signed-off-by: Qixiang Lin <qixiangl@nvidia.com>
Signed-off-by: Jhao-Ting Chen <jhaotingc@nvidia.com>
Co-authored-by: Qixiang Lin <qixiangl@nvidia.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: Yongye Zhu <zyy1102000@gmail.com>

2026-08-13 17:42:00 -07:00

..

__init__.py

[Core] Ensure memory is pinned prior to async h2d copy (#45424)

2026-06-20 20:02:24 -07:00

cpu.py

[Platform] Add check_runner_kv_caches_multi_layer (#51633)

2026-08-13 19:25:07 +00:00

cuda.py

[Platform] Add check_runner_kv_caches_multi_layer (#51633)

2026-08-13 19:25:07 +00:00

interface.py

[Kernel] Gemma-4 FA4 FP8 Kernel (#48666)

2026-08-13 17:42:00 -07:00

rocm.py

[Platform] Add check_runner_kv_caches_multi_layer (#51633)

2026-08-13 19:25:07 +00:00

tpu.py

[Refactor][TPU] Remove torch_xla path and use tpu-inference (#30808)

2026-01-07 16:07:16 +08:00

xpu.py

[Platform] Add check_runner_kv_caches_multi_layer (#51633)

2026-08-13 19:25:07 +00:00

zen_cpu.py

[ZenCPU] AMD Zen CPU Backend with supported dtypes via zentorch weekly (#39967)

2026-04-18 06:22:37 +00:00