Li, Jiang a15a50fc17 [CPU] Enable shared-memory based pipeline parallel for CPU backend (#21289) ...

Signed-off-by: jiang1.li <jiang1.li@intel.com>

2025-07-21 09:07:08 -07:00

..

multiprocessing

[Deprecation] Remove inputs arg fallback in Engine classes (#18799)

2025-06-09 10:19:56 +08:00

output_processor

[V0 Deprecation] Remove V0 Spec Decode workers (#21152)

2025-07-18 21:47:50 -07:00

__init__.py

Change the name to vLLM (#150)

2023-06-17 03:07:40 -07:00

arg_utils.py

[CPU] Enable shared-memory based pipeline parallel for CPU backend (#21289)

2025-07-21 09:07:08 -07:00

async_llm_engine.py

[Deprecation] Remove inputs arg fallback in Engine classes (#18799)

2025-06-09 10:19:56 +08:00

async_timeout.py

[Misc] Add SPDX-FileCopyrightText (#19100)

2025-06-03 11:20:17 -07:00

llm_engine.py

[V0 Deprecation] Remove V0 Spec Decode workers (#21152)

2025-07-18 21:47:50 -07:00

metrics_types.py

[V0 Deprecation] Remove V0 Spec Decode workers (#21152)

2025-07-18 21:47:50 -07:00

metrics.py

[V0 Deprecation] Remove V0 Spec Decode workers (#21152)

2025-07-18 21:47:50 -07:00

protocol.py

Elastic Expert Parallel Initial Support (#20775)

2025-07-18 17:46:09 -07:00