Chaojun Zhang 2725c84aae [XPU] Enable sequence parallel support for XPU (#38608) ...

Signed-off-by: chaojun-zhang <chaojun.zhang@intel.com>
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>

2026-06-14 19:26:46 -07:00

..

fusion

[XPU] Enable sequence parallel support for XPU (#38608)

2026-06-14 19:26:46 -07:00

ir

Preserve layout-changing clones (#44574)

2026-06-05 20:45:24 -04:00

utility

Speed up docs build (#44635)

2026-06-05 14:51:44 +00:00

__init__.py

[torch.compile] Reorganize vllm/compilation and tests/compile (0/N for vLLM IR) (#33731)

2026-02-06 04:19:49 -08:00

fx_utils.py

[torch.compile] Reorganize vllm/compilation and tests/compile (0/N for vLLM IR) (#33731)

2026-02-06 04:19:49 -08:00

inductor_pass.py

Speed up docs build (#44635)

2026-06-05 14:51:44 +00:00

pass_manager.py

[XPU] Enable sequence parallel support for XPU (#38608)

2026-06-14 19:26:46 -07:00

vllm_inductor_pass.py

[Aiter][ROCm] RMSNormGated+GroupedQuantFP8 fusion (#40710)

2026-05-14 15:37:09 -04:00