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vLLM/vllm/kernels
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Yintong LuYongqi WangKunshang Ji
72297d859b [XPU] Route weightless RMSNorm to _C dispatch (#47121)
Signed-off-by: Yintong Lu <yintong.lu@intel.com>
Co-authored-by: Yongqi Wang <yongqi.wang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
2026-07-29 18:59:58 +08:00
..
helion
[Kernel][Helion] Disable warp specialization in rms_norm_per_block_quant B200 configs (#48797)
2026-07-17 21:39:09 +00:00
triton
[Perf] FP8 FlashInfer Attn for ViT (#38065)
2026-04-27 13:44:15 +08:00
__init__.py
[vLLM IR] 1/N Implement IR skeleton and rms_norm op (#33825)
2026-03-31 22:15:05 -04:00
aiter_ops.py
[vLLM IR] 2/N fused_add_rms_norm and maybe_inplace overload (#36823)
2026-05-01 23:41:15 -04:00
oink_ops.py
[vLLM IR] 2/N fused_add_rms_norm and maybe_inplace overload (#36823)
2026-05-01 23:41:15 -04:00
vllm_c.py
[ROCm] Make vllm_c RMSNorm output contiguous (#49913)
2026-07-26 23:59:14 -05:00
xpu_ops.py
[XPU] Route weightless RMSNorm to _C dispatch (#47121)
2026-07-29 18:59:58 +08:00
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