Chaojun ZhangandKunshang Ji bf4f633b4c [XPU] Enable QK Norm + RoPE fusion pass on XPU (#49394) ...

Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>

2026-07-27 03:22:29 +00:00

..

__init__.py

[Core] Ensure memory is pinned prior to async h2d copy (#45424)

2026-06-20 20:02:24 -07:00

cpu.py

[CPU] fixes heterogeneous NIXL KV transfer into CPU_ATTN decode workers (#47871)

2026-07-20 07:33:13 +00:00

cuda.py

[Bugfix] Fix WSL circular import from pin_memory warning_once (#48444)

2026-07-20 18:30:55 -07:00

interface.py

[Bugfix] Fix WSL circular import from pin_memory warning_once (#48444)

2026-07-20 18:30:55 -07:00

rocm.py

[2/N][KV-Cache Layout Refactor] Pack K/V into the content dim across attention backends (#44455)

2026-07-11 11:11:16 -04:00

tpu.py

[Refactor][TPU] Remove torch_xla path and use tpu-inference (#30808)

2026-01-07 16:07:16 +08:00

xpu.py

[XPU] Enable QK Norm + RoPE fusion pass on XPU (#49394)

2026-07-27 03:22:29 +00:00

zen_cpu.py

[ZenCPU] AMD Zen CPU Backend with supported dtypes via zentorch weekly (#39967)

2026-04-18 06:22:37 +00:00