djramicandAndreas Karatzas 5fcc6e7c73 [ROCm][Bugfix] Fix TileLang mHC fused RMSNorm on 64-wide wavefronts (#58419) ...

Signed-off-by: Djordje Ramic <djoramic@amd.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>

2026-09-23 23:03:45 +00:00

..

__init__.py

[ROCm][DSV4.1][Perf] Use AITER mHC for the delayed pre block (#56503)

2026-09-12 00:35:48 +00:00

aiter.py

Add pydocstyle to the ruff rules (#52136)

2026-09-16 16:44:29 +00:00

cpu.py

[Model] Add DeepSeek-V4 CPU backend (#55355)

2026-09-10 14:14:48 +08:00

tilelang_kernels.py

[ROCm][Bugfix] Fix TileLang mHC fused RMSNorm on 64-wide wavefronts (#58419)

2026-09-23 23:03:45 +00:00

tilelang.py

Add pydocstyle to the ruff rules (#52136)

2026-09-16 16:44:29 +00:00

torch.py

Add pydocstyle to the ruff rules (#52136)

2026-09-16 16:44:29 +00:00

triton.py

[ROCm][DSV4.1][Perf] Use AITER mHC for the delayed pre block (#56503)

2026-09-12 00:35:48 +00:00

warmup.py

[Perf][DSV4.1] Overlap mHC coefficients for small TP batches (#57603)

2026-09-20 17:33:17 -07:00